ISL8016 Datasheet, PDF (20/22 Pages) Intersil Corporation – 6A Low Quiescent Current High Efficiency Synchronous Buck Regulator

ISL8016
where GM is the sum of the trans-conductance, g_m, of the
voltage error amplifier in each phase. Compensator capacitor C₆
is then given by:
C₆ = -_R----₆--¹-_ω----_c---_z- ,C₇= -₂---_π----_R---¹-₆----_f--_e---_s---_r
(EQ. 17)
Example: V_IN = 5V, V_o = 2.5V, I_o = 6A, fs = 1MHz, C_o = 44µF/3mΩ,
SL_n^{==12µ.H5,5G}×^M10=5V1/0s0,µf_c^s,=R1t0=00k.H2z5,Vt/hAen, ^VcFo^Bm=p0e.n6sVa,tSo^er
= 0.15V/µs,
resistance
R₆ = 120kΩ.
Put the compensator zero at 1.5kHz (~1.5x C_oR_o), and put the
compensator pole at ESR zero which is 390kHz. The
compensator capacitors are:
C₆ = 220pF, C₇ = 3pF (there is approximately 3pF parasitic
capacitance from V_COMP to GND; therefore, C₇ optional).
Figure 42 shows the simulated loop gain response. It is shown
that it has 95kHz loop bandwidth with 79° phase margin and at
least 10dB gain margin.
60
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8016, the power
loop is composed of the output inductor L’s, the output capacitor
C_OUT, the PHASE’s pins, and the PGND pin. It is necessary to
make the power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the PHASE pins, and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin , and the
ground of the input and output capacitors should be connected
as close as possible. The heat of the IC is mainly dissipated
through the thermal pad. Maximizing the copper area connected
to the thermal pad is preferable. In addition, a solid ground plane
is helpful for better EMI performance. It is recommended to add
at least 5 vias ground connection within the pad for the best
thermal relief.
45
30
GAIN LOOP (dB)
15
0
-15
-30
100
1k
10k
100k
1M
180
150
120
PHASE LOOP (°)
90
60
30
0
100
1k
10k
100k
1M
FIGURE 42. SIMULATED LOOP GAIN
20
FN7616.0
March 31, 2011