ISL6740IV-T Datasheet, PDF (20/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
Waveforms
Typical waveforms can be found in the following Figures. Figure
13 shows the output voltage during start up.
FIGURE 13. OUTPUT SOFT-START
Figure 14 shows the output voltage ripple and noise at a 5A load.
FIGURE 15. FET DRAIN-SOURCE VOLTAGE
FIGURE 16. FET D-S VOLTAGE NEAR-ZVS TRANSITION
FIGURE 14. OUTPUT RIPPLE AND NOISE (20MHz BW)
Figures 15 and 16 show the voltage waveforms at the switching
node shared by the upper FET source and the lower FET drain. In
particular, Figure 16 shows near ZVS operation at 8A of load when
the upper FET is turning off and the lower FET turning on. There is
insufficient energy stored in the leakage inductance to allow
complete ZVS operation. However, since the energy stored in the
node capacitance is proportional to V², a significant portion of the
energy is still recovered. Figure 17 shows the switching transition
between outputs, OUTA and OUTB during steady state operation.
The deadtime duration of 48.6ns is clearly shown.
FIGURE 17. OUTA TO OUTB TRANSITION
20
FN9111.6
December 2, 2011