ISL5585 Datasheet, PDF (20/22 Pages) Intersil Corporation – 3.3V Ringing SLIC Family for Voice Over Broadband VOB

ISL5585
TABLE 2. ISL5585 3V APPLICATION CIRCUIT COMPONENTS
COMPONENT
VALUE
TOL RATING
U1 - Ringing SLIC
ISL5585
N/A
N/A
R_TL
18.7kΩ
1%
0.1W
R_RT
23.7kΩ
1%
0.1W
R_SH
49.9kΩ
1%
0.1W
R_IL
71.5kΩ
1%
0.1W
R_S
66.5kΩ
1%
0.1W
R_F
30.1kΩ
1%
0.1W
R_A
36.5kΩ
1%
0.1W
R_B
42.2KkΩ
1%
0.1W
R_IN
45.3kΩ
1%
0.1W
C_RS, C_TX, C_RT, C_POL
0.47µF
20%
10V
C_DC, C_FB
4.7µF
20%
6.3V
C_PS1
0.1µF
20%
>100V
C_PS2, C_PS3
0.1µF
20%
100V
D₁
1N400X type with breakdown > 100V.
R_P1, R_P2
Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
Design Parameters: Ring Trip Threshold = 76mA_PEAK, Switch Hook
Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device
Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω protection
resistors, impedance across Tip and Ring terminals = 599Ω.
Transient current limit = 95mA.
Special Considerations for the QFN
Package
The new Quad Flatpack No-lead (QFN) package offers a
significant footprint reduction (65%) and improved thermal
performance with respect to the 28 lead PLCC. To realize
the thermal enhancements and maintain the high voltage
(-100V) performance, the exposed pad on the bottom of the
QFN package should be soldered to a power/heat sink plane
that is electrically connected to the ISL5585 Substrate
Common Connection (SCC) pin. The heat is distributed
evenly across the board by way of the heat sink plane. This
is accomplished by using conductive thermal vias.
Reference technical brief TB379 and AN9922 for additional
information on thermal characterization and board layout
considerations.
+
V_2W
-
C_PS1
C_PS2
C_PS3
D₁ 1N4004
CODEC
R_P1
49.9Ω
600Ω ^RP2
49.9Ω
C_RT
R_RT
R_SH
R_IL
C_DC
VCC VBL VBH
TIP
AUX
U₁
VTX
RING
ISL5585 -IN
RT
SH
ILIM
VFB
CDC
POL
C_RS
VRS
AGND
TL
BGND
0.47uF
R_S ^66.5kΩ
R_A
36.5kΩ
R_IN
30.1kΩ RF
0.47uF R_B
42.2kΩ
-
+
TX IN
Digital
Gain
0dB
+2.4V
45.3kΩ 0.47uF
C_FB
C_POL
PCM to V_2W Gain = +3.33dB, digital gain set to 0dB
V_CC
V_2W to PCM Gain = -9.3 dB, digital gain set to 0dB
0 dBm0, CODEC output voltage = 0.531Vrms
0 dBm0, V_2W = 0.7795Vrms
Digital
Gain
0dB
R_TL
Design Equations
R_S = 133.33(Z_L - 2R_P)
Gain PCM to V_2W = R_S/R_IN = 66.5k/45.3k =1.46
dB Gain =20log (0.7795/ 0.531) = +3.33dB
V_2W to PCM Gain = V_2W (G_2-4)(R_F/R_A) = (0.7795)(0.416)(30.1k/36.5k) = 0.267
dB Gain =20log (0.267/0.7795) = - 9.3dB
PCM
PCM
FIGURE 17. ISL5585 3.3V APPLICATION CIRCUIT
20