X4643 Datasheet, PDF (2/21 Pages) Xicor Inc. – CPU Supervisor with 64K EEPROM

X4643, X4645
PIN CONFIGURATION
8-Pin JEDEC SOIC
S₀ ¹
S₁ 2
RESET/RESET ³
V_SS 4
8 V_CC
7 _WP
6 SCL
5 SDA
8 Pin TSSOP
WP ¹
V_CC
2
S₀
3
S₁ 4
8 SCL
7 SDA
6
V_SS
5 RESET/RESET
PIN FUNCTION
Pin
(SOIC)
1
2
3
4
5
6
7
8
Pin
(TSSOP)
3
4
5
6
7
8
1
2
Name
S₀
S₁
RESET/RESET
V_SS
SDA
SCL
WP
V_CC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V_CC falls below the minimum V_CC sense level. It
will remain active until V_CC rises above the minimum V_CC sense level for
250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA
remains either HIGH or LOW longer than the selectable Watchdog time out pe-
riod. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer.
RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) re-
starts the Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
2
FN8123.0
March 29, 2005