TB386 Datasheet, PDF (2/3 Pages) Intersil Corporation – Implementing the HIP1011 on Hot Swap CPCI Boards for High Availability (HA) Platforms

Technical Brief 386
The extraction process begins with the opening of the
ejector handle. The SW connection control drives ENUM#
low to indicate impending extraction of the board. The OS
initiates the quiescing of I/O activity and disassociation from
the board. An LED lights to indicate the H2 / S0 state has
been reached and that removal can continue. The SW now
electrically isolates the board by asserting PCI_RST# and
deasserting BD_SEL#. Once the back end power drops,
HEALTHY# is pulled up indicating the board has been
powered down. The board is now electrically cold and ready
for complete removal.
HA Failed Process
Figure 3 illustrates the progression of a Board failure.
P0
PHYSICAL BOARD INSERTION
P1 H0
BD_SEL# ^{BOARD SEATED AND}
POWERED-ON
H1 H1F
H2 S0
HEALTHY # BOARD CANNOT SIGNAL HEALTHY
STATUS UPON POWER-UP OR
POWER FAILS DURING OPERATION.
RESULTS IN BD_SEL# SIGNAL
CYCLING OR BOARD
REPLACEMENT.
S1
S2 S2Q
S3 S3Q
BOARD EXHIBITS NORMAL ACTIVITY
THEN FAILS THUS GOING TO H1F STATE.
FIGURE 3.
Once the system manager recognizes complete board
insertion by the BD_SEL# (shortest pin) signal being pulled
up to V(I/O) it signals that pin low which turns on the
HIP1011. During power-up, if a failure occurs such that
HEALTHY# remains high indicating to the system manager
HW that the board has experienced a failure and cannot be
successfully powered-up. The HW manager then either
resets and retries a start-up cycle or returns to the P0 state
for board replacement.
At anytime during normal operation a failure can occur,
resulting in a board being put into a H1F state with the
HEALTHY# signal high indicating failure.
Controlling the Connection Process
As a specified enhancement in order to provide inter
operability for all HA platforms, all Hot Swap boards must
support the following signals. All of these signal
considerations have been included in the HIP1011BEVAL5
demo board shown in Figure 4. The components and
circuitry referenced below can also be found in Figure 4.
BD_SEL#
BD_SEL# is now an addressable signal in HA platforms. This
signal is on 1 of 2 shortest pins. Thus upon sensing and
subsequent addressing, all other pins have been connected
and are stable. This pin is pulled high to V(I/O) by HW and
signaled low to enable power-on. This is accomplished on the
HIP1011BEVAL5 demo board through R5 and the inverting
buffer on the HIP1011 PWRON pin along with SW1 simulating
the signal. This enhancement to CPCI boards provides single
board power control at any time necessary to the Hot Swap
Controller.
HEALTHY#
A second signal has been added for HW control and is used
to signal that a board has successfully powered-on and is
ready to be released from reset and allowed onto the PCI
bus. On the HIP1011BEVAL5 demo board this signal is
generated by sensing the states of the FLTN, PWRON and
3VISEN pins of the HIP1011. This provides feedback from
the 3 areas of concern: fault status, input state and output
state respectively. HEALTHY# is low when all requirements
are met. The HEALTHY# signal has a minimum requirement
of monitoring the ‘PGOOD’ of the boards power supply and
can be expanded to include other criteria.
Local_PCI_RST#
The third required signal is the Local_PCI_RST# signal, this
signal is asserted after HEALTHY# is valid and the system
generated PCI_RST# signal is also asserted.
Local_PCI_RST# must be deasserted immediately with the
loss of HEALTHY#.
BD_SEL#
+12VOUT
+5VOUT
+3.3VOUT
-12VOUT
5V/DIV.
10MS/DIV.
HEALTHY#
FIGURE 4.
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