ISL6744A Datasheet, PDF (2/18 Pages) Intersil Corporation – Intermediate Bus PWM Controller

Internal Architecture
V_DD
GND
UVLO
+
-
INTERNAL
BG
OT SHUTDOWN
130 - 150 C
V_BIAS
5.00 V
V_BIAS
R_TD
I_RTD
V_BIAS
160 uA
ON
C_T
2.0 V
2.8 V
0.8 V
-
PEAK
+
-
VALLEY
+
CLK
SQ
RQ
RESET
DOMINANT
I_DCH
ON
CS
+
OC DETECT
0.6 V -
SS COMPARATOR
C_T
+
-
SS
0.8
FL
Q
T
Q
PWM TOGGLE
SS CLAMP
-
+
V_BIAS
+
-
4.0 V
SS CHARGED
SQ
RQ
OC LATCH
V_DD
OUTA
V_BIAS
ON
OUTB
70uA
+
-
3.9 V
SS
15 uA
Q
50 µS
Q
RETRIGGERABLE
ONE SHOT
SQ
RQ
PWM LATCH
SET
DOMINANT
V_BIAS UV
4.65V ↓ 4.80V ↑
SS LOW
+ 0.27 V
-
SS
FAULT LATCH
SET DOMINANT
SQ
FL
RQ
-
+
BG
V_BIAS