ISL6144 Datasheet, PDF (2/29 Pages) Intersil Corporation – High Voltage ORing MOSFET Controller

ISL6144
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6144IVZA*
ISL61 44IVZ
-40 to +105
16 Ld TSSOP
M16.173
ISL6144IRZA*
ISL6144 IRZ
-40 to +105
20 Ld 5x5 QFN
L20.5x5
ISL6441EVAL1
Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinouts
ISL6144
(16 LD TSSOP)
TOP VIEW
ISL6144
(20 LD 5x5 QFN)
TOP VIEW
GATE 1
VIN 2
HVREF 3
NC ⁴
NC ⁵
NC ⁶
NC ⁷
GND ⁸
16 VOUT
15 COMP
14 VSET
13 NC
12 NC
11 NC
10 NC
9 FAULT
20 19 18 17 16
VIN 1
HVREF 2
NC 3
NC 4
NC 5
15 VOUT
14 COMP
13 VSET
12 NC
11 NC
6 7 8 9 10
Pin Descriptions
TSSOP
PIN #
1
QFN
PIN #
19
2
1
3
2
8
7
9
9
14
13
15
14
16
15
4, 5, 6, 7, 10, 3, 4, 5, 6, 8, 10,
11, 12, 13 11, 12, 16, 17,
18, 20
SYMBOL
GATE
VIN
HVREF
GND
FAULT
VSET
COMP
VOUT
NC
FUNCTION
DESCRIPTION
External FET Gate Drive
Allows active control of external N-Channel FET gate to perform
ORing function.
Power Supply Connection
Chip bias input. Also provides a sensing node for external FET
control.
Chip High Voltage Reference
Low side of floating high voltage reference for all of the HV chip
circuitry.
Chip Ground Reference
Chip ground reference point.
Fault Output
Provides an open drain active low output as an indication that a
fault has occurred: GATE is OFF (GATE < V_IN + 0.37V) or other
types of faults resulting in V_IN - V_OUT > 0.41V.
Low Side Connection for Trip Level Resistor connected to COMP provides adjustable “Vd - Vs” trip
level along with pin COMP.
High Side Connection for HS
Comparator Trip Level
Resistor connected to V_OUT provides sense point for the
adjustable Vd - Vs trip level along with pin VSET.
Chip Bias and Load Connection Provides the second sensing node for external FET control and
chip output bias.
No Connection
2
FN9131.5
October 8, 2010