ISL28107_09 Datasheet, PDF (2/22 Pages) Intersil Corporation – Precision Single and Dual Low Noise Operational Amplifiers

ISL28107, ISL28207
Ordering Information
PART NUMBER
(Notes 1, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28207FBZ
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FBZ-T7 (Note 2)
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28207FBZ-T13 (Note 2)
28207 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T7 (Note 2)
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T13 (Note 2)
28107 FBZ
-40 to +125
8 Ld SOIC
M8.15E
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. “-T7” and “-T13” suffix is for tape and reel. Please refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28107 and ISL28207. For more information on
MSL please see techbrief TB363.
Pin Configurations
ISL28107
(8 LD SOIC)
TOP VIEW
ISL28207
(8 LD SOIC)
TOP VIEW
NC 1
8 NC
-IN_A 2
-+
7 V+
+IN_A 3
6 V_OUTA
V- 4
5 NC
V_OUTA 1
8 V+
-IN_A 2 _{- +}
7 V_OUTB
+IN_A 3
+ - ^{6 -IN_B}
V- 4
5 +IN_B
Pin Descriptions
ISL28107
(8 LD SOIC)
3
4
7
6
2
1, 5, 8
ISL28207
(8 LD SOIC)
3
4
5
6
7
8
1
2
500Ω
IN-
500Ω
V+
IN+
V-
CIRCUIT 1
PIN
NAME
+IN_A
V-
+IN_B
-IN_B
V_OUTB
V+
V_OUTA
-IN_A
NC
EQUIVALENT
CIRCUIT
Circuit 1
Circuit 3
Circuit 1
Circuit 1
Circuit 2
Circuit 3
Circuit 2
Circuit 1
-
DESCRIPTION
Amplifier A non-inverting input
Negative power supply
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
Positive power supply
Amplifier A output
Amplifier A inverting input
No internal connection
V+
OUT
V-
CIRCUIT 2
V
CAPACITIVELY
TRIGGERED
V-
CIRCUIT 3
2
FN6631.1
November 16, 2009