ISL23418_15 Datasheet, PDF (2/20 Pages) Intersil Corporation – Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

Block Diagram
V_LOGIC
ISL23418
V_CC
SCK
POWER-UP
RH
SDI
SDO
CS
I/O BLOCK
LEVEL
SHIFTER
INTERFACE,
CONTROL
AND
STATUS
WR
VOLATILE
REGISTER
LOGIC
AND
WIPER
CONTROL
CIRCUITRY
Pin Configurations
V_LOGIC
SCK
SDO
SDI
CS
ISL23418
(10 LD MSOP)
TOP VIEW
1O
10
2
9
3
8
4
7
5
6
GND
V_CC
RH
RW
RL
ISL23418
(10 LD µTQFN)
TOP VIEW
O
SCK 1
SDO 2
SDI 3
CS 4
9 GND
8 V_CC
7 RH
6 RW
RL
RW
GND
Pin Description
MSOP
1
µTQFN
10
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
SYMBOL
DESCRIPTION
V_LOGIC SPI bus/logic supply; range 1.2V to
5.5V
SCK Logic pin: serial bus clock input
SDO Logic pin: serial bus data output
(configurable)
SDI Logic pin: serial bus data input
CS Logic pin: active low Chip Select
RL DCP “low” terminal
RW DCP wiper terminal
RH DCP “high” terminal
V_CC Analog power supply; range 1.7V to
5.5V
GND Ground pin
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FN7901.1
September 24, 2015