ISL22346WM_14 Datasheet, PDF (2/3 Pages) Intersil Corporation – Low Noise, Low Power I2C® Bus, 128 Taps

ISL22346WM
Block Diagram
SCL
SDA
A0
A1
A2
I²C
INTERFACE
SHDN
V_CC
POWER-UP
INTERFACE,
CONTROL
AND STATUS
LOGIC
NON-
VOLATILE
REGISTERS
WR3
WR2
WR1
WR0
RH3
RW3
RL3
RH2
RW2
RL2
RH1
RW1
RL1
RH0
RW0
RL0
Pin Descriptions
TSSOP PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
RW1
RL1
RH1
A0
A1
VCC
SHDN
RH0
RL0
RW0
GND
DESCRIPTION
“High” terminal of DCP3
“Low” terminal of DCP3
“Wiper” terminal of DCP3
Device address input for the I²C interface
Open drain I²C interface clock input
Open drain Serial data I/O for the I²C interface
Device ground pin
“Wiper” terminal of DCP2
“Low” terminal of DCP2
“High” terminal of DCP2
“Wiper” terminal of DCP1
“Low” terminal of DCP1
“High” terminal of DCP1
Device address input for the I²C interface
Device address input for the I²C interface
Power supply pin
Shutdown active low input
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
2
FN6624.1
November 11, 2011