HFA3102_05 Datasheet, PDF (2/8 Pages) Intersil Corporation – Dual Long-Tailed Pair Transistor Array

HFA3102
Absolute Maximum Ratings T_A = 25°C
V_CEO Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . 8.0V
V_CBO Collector to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . 12.0V
V_EBO Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . 12.0V
I_C, Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Thermal Information
Thermal Resistance (Typical, Note 1)
θ_JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
Maximum Power Dissipation at 75°
Any One Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.25W
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications T_A = 25°C
SYMBOLS
PARAMETER
TEST CONDITIONS
(NOTE 2)
TEST
LEVEL
ALL GRADES
MIN TYP MAX
UNITS
V_(BR)CBO
V_(BR)CEO
V_(BR)EBO
I_CBO
I_EBO
h_FE
C_CB
C_EB
f_T
f_MAX
G_NFMIN
Collector-to-Base Breakdown Voltage (Q₁, I_C = 100µA, I_E = 0
Q₂, Q₄, and Q₅)
Collector-to-Emitter Breakdown
Voltage (Q₁ thru Q₆)
I_C = 100µA, I_B = 0
Emitter-to-Base Breakdown Voltage (Q₃
and Q₆)
I_E = 50µA, I_C = 0
Collector Cutoff Current
(Q₁, Q₂, Q₄, and Q₅)
V_CB = 5V, I_E = 0
Emitter Cutoff Current (Q₃ and Q₆)
V_EB = 1V, I_C = 0
DC Current Gain (Q₁ thru Q₆)
I_C = 10mA, V_CE = 3V
Collector-to-Base Capacitance
V_CB = 5V, f = 1MHz
Emitter-to-Base Capacitance
V_EB = 0, f = 1MHz
Current Gain-Bandwidth Product
I_C = 10mA, V_CE = 5V
Power Gain-Bandwidth Product
I_C = 10mA, V_CE = 5V
Available Gain at Minimum Noise Figure
I_C = 3mA,
V_CE = 3V
f = 0.5GHz
f = 1.0GHz
A
12
18
-
V
A
8
12
-
V
A
5.5
6
-
V
A
-
0.1
10
νΑ
A
-
-
100
νΑ
A
40
70
-
-
B
-
300
-
fF
B
-
200
-
fF
C
-
10
-
GHz
C
-
5
-
GHz
C
-
17.5
-
dB
C
-
12.4
-
dB
NF_MIN
Minimum Noise Figure
I_C = 3mA, f = 0.5GHz
C
V_CE = 3V _{f = 1.0GHz}
C
-
1.8
-
dB
-
2.1
-
dB
NF_50Ω 50Ω Noise Figure
I_C = 3mA, f = 0.5GHz
C
V_CE = 3V _{f = 1.0GHz}
C
-
3.3
-
dB
-
3.5
-
dB
h_FE1/h_FE2 DC Current Gain Matching
(Q₁ and Q₂, Q₄ and Q₅)
I_C = 10mA, V_CE = 3V
A
0.9
1.0
1.1
-
V_OS
Input Offset Voltage (Q₁ and Q₂),
(Q₄ and Q₅)
I_C = 10mA, V_CE = 3V
A
-
1.5
5
mV
I_OS
Input Offset Current (Q₁ and Q₂),
(Q₄ and Q₅)
I_C = 10mA, V_CE = 3V
A
-
5
25
µA
dV_OS/dT
Input Offset Voltage TC
(Q₁ and Q₂, Q₄ and Q₅)
I_C = 10mA, V_CE = 3V
C
-
0.5
-
µV/°C
I_TRENCH- Collector-to-Collector Leakage
LEAKAGE ^{(Pin 6, 7, 13, and 14)}
∆V_TEST = 5V
B
-
0.01
-
nA
NOTE:
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only
2
FN3635.5
July 14, 2005