HD-6402 Datasheet, PDF (2/7 Pages) Intersil Corporation – CMOS Universal Asynchronous Receiver Transmitter (UART)

Functional Diagram
(24) TRE
(22) TBRE †
(23) TBRL
(40) TRC
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
(17) RRC
(18) DRR
(19) DR †
TRANSMITTER
TIMING AND
CONTROL
RECEIVER
TIMING AND
CONTROL
(16) SFD
† THESE OUTPUTS ARE
THREE-STATE
† OE
(15)
HD-6402
(32) (30) (28) (26)
TBR8 (33) (31) (29) (27) TBR1
STOP
PARITY
LOGIC
TRANSMITTER BUFFER REGISTER
TRANSMITTER REGISTER
MULTIPLEXER
START
CONTROL
REGISTER
STOP
LOGIC
† FE
(14)
MULTIPLEXER
PARITY
LOGIC
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
START
LOGIC
3-STATE
BUFFERS
† PE
(13)
† RBR8
† RBR1
(5) (6) (7) (8) (9) (10) (11) (12)
(25) TRO
(36) SBS
(16) SFD
(39) EPE
(35) PI
(20) RRI
(4) RRD
Control Definition
CLS 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CONTROL WORD
CLS 1
PI
EPE
0
0
0
0
0
0
0
0
1
0
0
1
0
1
X
0
1
X
1
0
0
1
0
0
1
0
1
1
0
1
1
1
X
1
1
x
0
0
0
0
0
0
0
0
1
0
0
1
0
1
X
0
1
x
1
0
0
1
0
0
1
0
1
1
0
1
1
1
X
1
1
x
SBS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CHARACTER FORMAT
DATA BITS
PARITY BIT
5
ODD
5
ODD
5
EVEN
5
EVEN
5
NONE
5
NONE
6
ODD
6
ODD
6
EVEN
6
EVEN
6
NONE
6
NONE
7
ODD
7
ODD
7
EVEN
7
EVEN
7
NONE
7
NONE
8
ODD
8
ODD
8
EVEN
8
EVEN
8
NONE
8
NONE
STOP BITS
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2