CD54ACT299 Datasheet, PDF (2/2 Pages) Intersil Corporation – 8-Input Universal Shift/Storage Registers with Common Parallel I/O Pins

CD54AC299/3A
SEMICONDUCTOR
CD54ACT299/3A
COMPLETE DATA SHEET _{8-Input Universal Shift/Storage Registers}
June 1997
COMING SOON!
with Common Parallel I/O Pins
Description
The CD54AC299/3A and CD54ACT299/3A are three-state,
8-input universal shift/storage registers with common parallel
I/O pins. These devices utilize the Harris Advanced CMOS
Logic technology. These registers have four synchronous
operating modes controlled by the two select inputs as shown
in the Mode Select (S0, S1) table. The Mode Select, the Serial
Data (DS0, DS7), and the Parallel Data (I/O₀ - I/O₇) respond
only to the LOW-to-HIGH transition of the clock pulse (CP).
S0, S1 and Data inputs must be present one setup time prior
to the positive transition of the clock.
The Master Reset (MR) is an asynchronous active-LOW
input. When MR is LOW, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (QO) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is accom-
plished by tying the Q7 of the last stage to the DS0 of the
first stage.
The three-state input/output (I/O) port has three modes of
operation
2. When both S0 and S1 are HIGH, I/O terminals are in the
high-impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two Output Enable inputs being HIGH
will force I/O terminals to be in the off state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
The CD54AC299/3A and CD54ACT299/3A are supplied in
20 lead dual-in-line ceramic packages (F suffix).
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD (NOTE 1)
S1, S2, OE1, OE2
0.83
SL, CP
0.67
MR
1.33
NOTE:
1. Unit load is ∆I_CC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA Max at +25^oC.
1. Both Output Enable (OE1 and OE2) inputs are LOW and
S0 or S1 or both are LOW, the data in the register is
present at the eight outputs.
Functional Diagram
CP OE1 OE2 MR
12
2
3
9
THREE-STATE
CONTROL
20 V_CC
I/O₀ 7
BUS LINE ^{I/O2 6}
OUTPUTS _{I/O4 5}
I/O₆ 4
STANDARD OUTPUT Q0 8
S0 1
I/O
THREE-STATE
OUTPUTS
SHIFT
REGISTER
I/O
THREE-STATE
OUTPUTS
10
GND
MODE
SELECTION
11 18
DS0 DS7
13 I/O₁
14 I/O₃
15 I/O₅
BUS LINE
OUTPUTS
16 I/O₇
17 Q7 STANDARD OUTPUT
19 S1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
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File Number 3907