CD4011BT Datasheet, PDF (2/3 Pages) Intersil Corporation – CMOS Quad 2-Input NAND Gate

Schematic and Logic Diagram
CD4011BT
p
14 V_DD
1†
n
(8, 6, 13)
p
2†
n
(9, 5, 12)
n
V_DD
p
p
p
3 (10, 4, 11)
n
n
7 V_SS
† ALL INPUTS ARE PROTECTED
V_SS
BY CMOS PROTECTION NETWORK
1(8, 6,13)
2(9, 5, 12)
1 OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
3
(10, 4, 11)
LOGIC DIAGRAM
2