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BBT3421 Datasheet, PDF (2/2 Pages) Intersil Corporation – 4 Channel Multi-rate Intelligent CMOS Re-Timer
BBT3421
Data Flow
The BBT3421 re-timer accepts serial data from the CML
pins, performs clock and data recovery on the bit stream,
optionally scans the data for the “comma” patterns, Byte-
Aligns the data on either ‘disparity’ comma pattern, and de-
serializes the data. The data is then fed into the receive
FIFO, where clock compensation, and optional channel
alignment are performed. The parallel data is then
resynchronized into the Transmit FIFO using the local
reference clock, serialized to this local reference clock, and
sent out to the differential CML, XAUIcompatible TX pins.
In addition, several other facilities are provided to ease
system testing. Loop-back of the serial signals is available
under external pin or MII control. Suitable control and status
registers are available through the IEEE standard
MDIO/MDC system. If the Built-in-Self-Test function (BIST) is
in use, the serial TX data instead is derived from a PRBS
2^23 -1 pattern generator. In this BIST mode, the received
serial data is checked against the PRBS pattern transmitted
and, if an error is found, a flag signal is provided.
Channel 3
Channel 2
Channel 1
Channel 0
IN0-
Clock & Deserializer
IN0+
Data
& Comma
Recovery
Detector
8B/10B
Decoder
Receive
FIFO
Receive
Parallel
Data
8B/10B
Encoder
& Mux
OUT0-
OUT0+
RCLOCK NRCLOCK
Clock Multiplier
3.125G
Static
Controls
MDIO/MDC Register
File
MDIO
MDC
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF BBT3421
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