82C86H_04 Datasheet, PDF (2/6 Pages) Intersil Corporation – CMOS Octal Bus Transceiver

82C86H
Functional Diagram
Decoupling Capacitors
The transient current required to charge and discharge the
A0
300pF load capacitance specified in the 82C86H/87H data
B0
sheet is determined by:
A1
B1
I = C_L(dv ⁄ dt)
(EQ. 1)
A2
B2
Assuming that all outputs change state at the same time and
A3
B3
that dv/dt is constant;
A4
A5
B4
B5
I = C_L⁽---^V----^C----_t-^C-_R-----^×-_⁄--_t--⁸-_F--⁰----^%------⁾
(EQ. 2)
A6
B6
where tR = 20ns, V_CC = 5.0V, C_L = 300pF on each eight out-
puts.
A7
B7
I = (80 × 300 × 10^–12) × (5.0V × 0.8) ⁄ (20 × 10^–9)
(EQ. 3)
= 480mA
OE
T
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V_CC and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in device
operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V_CC and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V_CC to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V_IH or maximum
V_IL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
STB
DATA IN
V_CC
V_CC
P
P
N
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
V_CC
OE
DATA IN
P
P
INTERNAL
DATA
V_CC
N
P
N
N
FIGURE 2. 82C86H/87H GATED INPUTS
This current spike may cause a large negative voltage spike
on V_CC which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1µF
ceramic disc capacitor be placed between V_CC and GND at
each device, with placement being as near to the device as
possible.
2