ISL62881_10 Datasheet, PDF (19/35 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62881, ISL62881B
i_O
i_L
V_O
RING
BACK
FIGURE 17. OUTPUT VOLTAGE RING BACK PROBLEM
ISUM+
Rntcs
Rp
Rntc
Cn.1
Rn
OPTIONAL
+
Cn.2 Vcn
-
Ri ^ISUM-
Rip ^Cip
OPTIONAL
FIGURE 18. OPTIONAL CIRCUITS FOR RING BACK
REDUCTION
Figure 17 shows the output voltage ring back problem
during load transient response. The load current i_o has a
fast step change, but the inductor current i_L cannot
accurately follow. Instead, i_L responds in first order
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage V_o dip quickly upon load current change.
However, the controller regulates V_o according to the
droop current i_droop, which is a real-time representation
of i_L; therefore it pulls V_o back to the level dictated by i_L,
causing the ring back problem. This phenomenon is not
observed when the output capacitors have very low ESR
and ESL, such as all ceramic capacitors.
Figure 18 shows two optional circuits for reduction of the
ring back. R_ip and C_ip form an R-C branch in parallel with
R_i, providing a lower impedance path than R_i at the
beginning of i_o change. R_ip and C_ip do not have any
effect at steady state. Through proper selection of R_ip
and C_ip values, i_droop can resemble i_o rather than i_L, and
V_o will not ring back. The recommended value for R_ip is
100W. C_ip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for C_ip is 100pF~2000pF.
C_n is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more)
capacitors to get the desired value. Figure 18 shows
that two capacitors C_n.1 and C_n.2 are in parallel.
Resistor R_n is an optional component to reduce the V_o
ring back. At steady state, C_n.1 + C_n.2 provides the
desired C_n capacitance. At the beginning of i_o change,
the effective capacitance is less because R_n increases
the impedance of the C_n.1 branch. As Figure 15
explains, V_o tends to dip when C_n is too small, and this
effect will reduce the V_o ring back. This effect is more
pronounced when C_n.1 is much larger than C_n.2. It is
also more pronounced when R_n is bigger. However, the
presence of R_n increases the ripple of the V_n signal if
C_n.2 is too small. It is recommended to keep C_n.2
greater than 2200pF. R_n value usually is a few ohms.
C_n.1, C_n.2 and R_n values should be determined
through tuning the load transient response waveforms
on an actual board.
R_ip and C_ip form an R-C branch in parallel with R_i,
providing a lower impedance path than R_i at the
beginning of i_o change. R_ip and C_ip do not have any
effect at steady state. Through proper selection of R_ip
and C_ip values, i_droop can resemble i_o rather than i_L,
and V_o will not ring back. The recommended value for
R_ip is 100Ω. C_ip should be determined through tuning
the load transient response waveforms on an actual
board. The recommended range for C_ip is
100pF~2000pF. However, it should be noted that the
R_ip -C_ip branch may distort the i_droop waveform.
Instead of being triangular as the real inductor current,
i_droop may have sharp spikes, which may adversely
affect i_droop average value detection and therefore
may affect OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
PHASE
L
DCR
RSEN
RSUM
Vcn
ISUM+
Cn
Ri
ISUM-
Io
FIGURE 19. RESISTOR CURRENT-SENSING NETWORK
Figure 19 shows the resistor current-sensing network.
The inductor has a series current-sensing resistor R_sen.
R_sum and is connected to the R_sen pad to accurately
capture the inductor current information. The R_sum feeds
the sensed information to capacitor C_n. R_sum and C_n
19
FN6924.1
February 25, 2010