ISL6255_14 Datasheet, PDF (19/22 Pages) Intersil Corporation – Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers

ISL6255, ISL6255A
Vo
V_{FB -}
V_REF
g_m
+
V_COMP
R1
C1
FIGURE 18. VOLTAGE LOOP COMPENSATOR
Figure 17 shows the voltage loop compensator, and its
transfer function is expressed as follows:
A_v
(S)
=
vˆ _comp
vˆ _FB
1+ ^S
= g_m
ω _cz
SC₁
where
ω _cz
=
1
R₁C₁
Compensator design goal:
• High DC gain
•
Loop
bandwidth
f_c:
⎜⎛ ¹
⎝⁵
−
1
20
⎟⎞
⎠
f_s
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
1. Put compensator zero at
ω_cz
=
(1
−
3)
1
R_oC_o
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
esr zero frequency or half switching frequency, whichever
is lower.
The loop gain T_v(S) at cross over frequency of f_c has unity
gain. Therefore, the compensator resistance R₁ is
determined by:
R₁
=
82π
11
f_cV_oC_o R_T
g _mV_FB
where g_m is the trans-conductance of the voltage loop error
amplifier. Compensator capacitor C1 is then given by:
C₁
=
1
R₁ ω_cz
Example: V_in = 20V, V_o = 16.8V, I_o = 2.6A, f_s = 300kHz,
C_o = 10μF/10mΩ, L = 10μH, g_m = 250μs, R_T = 0.8Ω,
V_FB = 2.1V, f_c = 20kHz, then compensator resistance
R₁ = 10kΩ. Put the compensator zero at 1.5kHz. The
compensator capacitor is C₁ = 6.5nF. Therefore, choose
voltage loop compensator: R₁ = 10k, C₁ = 6.5nF.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces.The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
19
FN9203.2
May 23, 2006