ISL6721A_14 Datasheet, PDF (18/24 Pages) Intersil Corporation – Flexible Single-ended Current Mode PWM Controller

ISL6721A
page 4, the remaining pole and zero for the compensator are
located at (Equations 38, 39):
f_pc = ₂-----_•-----_π----_•---^C--_R---¹-₁--³-₅---+--_•---^C-_C----¹¹---⁴⁴-----_•----_C-----₁---₃- ≈ -₂----_•-----_π----_•-----_R--¹--₁---₅-----_•----_C----₁---₄--
(EQ. 38)
f_zc = ₂-----_•-----_π----_•-----_R--¹--₁---₅-----_•----_C----₁---₃--
(EQ. 39)
The ratio of R₁₅ to the parallel combination of R₁₇ and R₁₈
determine the mid band gain of the error amplifier
(Equation 40).
A_midband
=
-^R----¹---⁵----^•-----⁽--^R-----¹---⁷----+-----^R----¹---⁸----⁾
R₁₇ • R₁₈
(EQ. 40)
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum V_IN, maximum load, maximum C_OUT, and
minimum ESR.
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
to about f_sw/4. For this example, the bandwidth will be further
limited due to the low GBWP of the LM431-based Error
Amplifier and the opto-coupler. A bandwidth of approximately
5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C₁₄ is an integrating capacitor). The first
zero is placed below the crossover frequency, f_co, usually
around 1/3 f_co. The second pole is placed at the lower of the
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R₁₇ = R₁₈ = R₁₅ = 1kΩ
R₂₀ = open
C₁₃ = 100nF
C₁₄ = 100pF
A Bode plot of the closed loop system at low line, max load
appears in Figures 9A and 9B.
50
40
30
20
10
0
-10
-20
-30
-40
-50
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 9A. GAIN
100M
200
150
100
50
0
-50
-100
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 9B. PHASE MARGIN
100M
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, V_IN = 48V
I_OUT (A), 3.3V I_OUT (A), 1.8V V_OUT (V), 3.3V V_OUT (V), 1.8V
0
0.030
3.351
1.825
0.39
0.030
3.281
1.956
0.88
0.030
3.251
1.988
1.38
0.030
3.223
2.014
1.87
0.030
3.204
2.029
2.39
0.030
3.185
2.057
2.89
0030
3.168
2.084
3.37
0.030
3.153
2.103
0
0.52
3.471
1.497
0.39
0.52
3.283
1.800
0.88
0.52
3.254
1.836
1.38
0.52
3.233
1.848
1.87
0.52
3.218
1.855
2.39
0.52
3.203
1.859
2.89
0.52
3.191
1.862
0
1.05
3.619
1.347
0.39
1.05
3.290
1.730
18
FN6797.0
August 23, 2011