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| ISL6150_14 Datasheet, PDF (18/19 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller | |||
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GND
R6
R5
R4
-48VIN
ISL6140, ISL6150
C2
1 PG
VDD 8
R3
G
2 OV
U1
D7
3 UV
G6
R2
4 VEE
S5
C1
S
R1
GND
DRAIN
FET
-48VOUT
FIGURE 30. SAMPLE LAYOUT (NOT TO SCALE)
.
GND
GND
R4
UV
VDD
R5
ISL6140
OV
R6
VEE SENSE GATE
PWRGD
DRAIN
(LOAD)
C1 R2 R3
C2
CL
RL
-48V IN
R1
Q1
-48VOUT
FIGURE 31. TYPICAL APPLICATION
NOTES:
1. Layout scale is approximate; routing lines are just for
illustration purposes; they do not necessarily conform to
normal PCB design rules. High current buses are wider,
shown with parallel lines.
2. Approximate size of the above layout is 1.6 x 0.6 inches;
almost half of the area is just the FET (D2PAK or similar
SMD-220 package).
3. R1 sense resistor is size 2512; all other Râs and Câs shown
are 0805; they can all potentially use smaller footprints, if
desired.
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the
board; all other routing can be on top level. (Itâs even
possible to eliminate the via, for an all top-level route).
6. PWRGD signal is not used here.
7. BOM (Bill Of Materials)
R1 = 0.02Ω (5%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 562kΩ (1%)
R5 = 9.09kΩ (1%)
R6 = 10kΩ (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
18
FN9039.4
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