ISL6141_14 Datasheet, PDF (18/19 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6141, ISL6151
Applications: Layout Considerations
For the minimum application, there are only 6 resistors, 2
capacitors, one IC and one FET. A sample layout is shown in
Figure 35. It assumes the IC is 8-SOIC; the FET is in a
D2PAK (or similar SMD-220 package).
Although GND planes are common with multi-level PCBs, for
a -48V system, the -48V rails (both input and output) act
more like a GND than the top 0V rail (mainly because the IC
signals are mostly referenced to the lower rail). So if
separate planes for each voltage are not an option, consider
prioritizing the bottom rails first.
Note that with the placement shown, most of the signal lines
are short, and there should not be minimal interaction
between them.
Although decoupling capacitors across the IC supply pins
are often recommended in general, this application may not
need one, nor even tolerate one. For one thing, a decoupling
cap would add to (or be swamped out by) any other input
capacitance; it also needs to be charged up when power is
applied. But more importantly, there are no high speed (or
any) input signals to the IC that need to be conditioned. If still
desired, consider the isolation resistor R10, as shown in
Figure 34.
GND
GND
C2
R6
1 PG
VDD 8
R3
G
2 OV
U1
D7
R5
3 UV
G6
R2
4 VEE
S5
R4
R1
-48V IN
C1
S
DRAIN
FET
-48V OUT
GND
GND
R4
UV
V_DD
R5
ISL6141
OV
R6
V_{EE SENSE GATE}
PWRGD
DRAIN
(LOAD)
C1
R3
R2
C2
CL
RL
-48V IN
R1
Q1
-48V OUT
FIGURE 35. ISL6141/51 SAMPLE LAYOUT (NOT TO SCALE)
NOTES:
1. Layout scale is approximate; routing lines are just for illustration
purposes; they do not necessarily conform to normal PCB
design rules. High current buses are wider, shown with parallel
lines.
2. Approximate size of the above layout is 1.6 x 0.6 inches; almost
half of the area is just the FET (D2PAK or similar SMD-220
package).
3. R1 sense resistor is size 2512; all other R’s and C’s shown are
0805; they can all potentially use smaller footprints, if desired.
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the board; all
other routing can be on top level. (It’s even possible to eliminate
the via, for an all top-level route).
BOM (Bill Of Materials)
R1 = 0.02Ω (5%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 549kΩ (1%)
R5 = 6.49kΩ (1%)
R6 = 10kΩ (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
6. PWRGD signal is not used here.
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