HS-80C86RH Datasheet, PDF (18/37 Pages) Intersil Corporation – Radiation Hardened 16-Bit CMOS Microprocessor

HS-80C86RH
will be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns the
read signal to a HIGH level, the addressed device will three-
state its bus drivers. If a transceiver is required to buffer the
HS-80C86RH local bus, signals DT/R and DEN are provided
by the HS-80C86RH.
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO signal is again asserted
to indicate a memory or I/O write operation. In T2, immed-
iately following the address emission, the processor emits
the data to be written into the addressed location. This data
remains valid until at least the middle of T4. During T2, T3
and TW, the processor asserts the write control signal. The
write (WR) signal becomes active at the beginning of T2 as
opposed to the read which is delayed somewhat into T2 to
provide time for output drivers to become inactive.
The BHE and A0 signals are used to select the proper
byte(s) of the memory/IO word to be read or written accord-
ing to Table 11.
TABLE 11.
BHE
A0
CHARACTERISTICS
0
0 Whole word
0
1 Upper byte from/to odd address
1
0 Lower byte from/to even address
1
1 None
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the D7-D0
bus lines and odd address bytes on D15-D6.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge sig-
nal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus hold devices. (See Figure 4). In the second of two suc-
cessive INTA cycles a byte of information is read from the
data bus (D7-D0) as supplied by the interrupt system logic
(i.e. HS-82CS9ARH Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied by
four and used as a pointer into an interrupt vector Iookup
table, as described earlier.
Bus Timing - Medium and Large Size Systems
For medium complexity systems the MN/MX pin is
connected to GND and the 82C88 Bus Controller is added to
the system as well as three 82C82 latches for latching the
system address, and a transceiver to allow for bus loading
greater than the HS-80C86RH is capable of handling. Bus
control signals are generated by the 82C88 instead of the
processor in this configuration, although their timing remains
relatively the same. The HS-80C86RH status outputs (S2,
S1, and S0) provide type-of-cycle information and become
82C88 inputs. This bus cycle information specifies read
(code, data or I/O), write (data or I/O), interrupt acknowl-
edge, or software halt. The 82C88 issues control signals
specifying memory read or write, I/O read or write, or inter-
rupt acknowledge. The 82C88 provides two types of write
strobes, normal and advanced, to be applied as required.
The normal write strobes have data valid at the leading edge
of write. The advanced write strobes have the same timing
as read strobes, and hence, data is not valid at the leading
edge of write. The transceiver receives the usual T and 0E
inputs from the 82C88 DT/R and DEN signals.
For large multiple processor systems, the 82C89 bus arbiter
must be added to the system to provide system bus man-
agement. In this case, the pointer into the interrupt vector
table, which is passed during the second INTA cycle, can be
derived from an HS-82C59ARH located on either the local
bus or the system bus. The processor’s INTA output should
drive the SYSB/RESB input of the 82C89 to the proper state
when reading the interrupt vector number from the HS-
82C59ARH during the interrupt acknowledge sequence and
software “poll”.
A Note on Radiation Hardened Product Availability
There are no immediate plans to develop the 82C88 Bus
Controller or the 82C89 Arbiter as radiation hardened
integrated circuits.
A Note on SEU Capability of the HS-80C86RH
Previous heavy ion testing of the HS-80C86RH has indi-
cated that the SEU threshold of this part is about 6
MEV/mg/cm². Based upon these results and other analysis,
a deep space galactic cosmic-ray environment will result in
an SEU rate of about 0.08 upsets/day.
Spec Number 518055
873