ISLA214P12_14 Datasheet, PDF (17/34 Pages) Intersil Corporation – High Performance 14-Bit, 125MSPS ADC

ISLA214P12
Theory of Operation
Functional Description
The ISLA214P12 is based on a 14-bit, 125MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (see Figure 19). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 125MSPS the nominal calibration time is 560ms, while the
maximum calibration time is 1000ms.
CLOCK
GENERATION
INP
SHA
INN
+
1.25V
–
2.5- BIT
FLASH
2.5-BIT
FLASH
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1- BIT/ STAGE
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
3- BIT
FLASH
17
FN7982.2
June 27, 2012