ISL8273M Datasheet, PDF (17/55 Pages) Intersil Corporation – 80A Single Channel Digital PMBus Step-Down Power Module

ISL8273M
command ON_OFF_CONFIG, such that the internal MOSFETs are
turned off immediately after the delay time expires.
In the current sharing mode where multiple ISL8273M modules
are connected in parallel, ASCR is required to be disabled for the
ramp-up with the USER_CONFIG command. Therefore, the
soft-start rise time is not equal to TON_RISE. It can be calculated
approximately by Equation 1.
Rise Time (ms)  ^T---_V--^O--_I--_N-^N----_-^_---^R-_f--_S-^I--^S-_W---^E--  330kHz  12V
(EQ. 1)
Also in the current sharing mode, ASCR will be enabled
automatically upon power-good assertion after the ramp
completes. To avoid premature ASCR turn on, it is recommended
to increase POWER_GOOD_DELAY if the rise time exceeds 10ms.
In addition, only “immediate off” is supported for current sharing.
In the current sharing mode, if module self enable is used (VIN
power-up), a minimum TON_DELAY of 15ms is recommended.
The SS/UVLO pin can be used to program the soft-start/stop
delay time and ramp time to some typical values as shown in
Table 4.
TABLE 4. SOFT-START/STOP RESISTOR SETTINGS
DELAY TIME
(ms)
RAMP TIME
(ms)
R_SET
(kΩ)
5
2
19.6, or Connect to
SGND
10
2
21.5
5
5
23.7, or OPEN
10
5
26.1
20
5
28.7
5
10
31.6
10
10
34.8, or Connect to V25
20
10
38.3
5
2
42.2
10
2
46.4
5
5
51.1
10
5
56.2
20
5
61.9
5
10
68.1
10
10
75
20
10
82.5
Power-Good
The ISL8273M provides a Power-good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within 10% of the target voltage. This limit may be
changed using the PMBus command POWER_GOOD_ON.
A PG delay period is defined as the time from when all conditions
within the ISL8273M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
A PG delay can be programmed using the PMBus command
POWER_GOOD_DELAY.
Switching Frequency and PLL
The device’s switching frequency is set from 296kHz to 1067kHz
using the pin-strap method (for stand-alone noncurrent sharing
module only) as shown in Table 5, or by using the PMBus
command FREQUENCY_SWITCH. The ISL8273M incorporates an
internal Phase-locked Loop (PLL) to clock the internal circuitry.
The PLL can be driven by an external clock source connected to
the SYNC pin. It is recommended that when using an external
clock, same frequency should be set in the FREQUENCY_SWITCH
command. In case the external clock is lost, the module will
automatically switch to the internal clock. When using the
internal oscillator, the SYNC pin can be configured as a clock
source and as external sync to other modules. Refer to
SYNC_CONFIG command on page 47 for more information.
TABLE 5. SWITCHING FREQUENCY RESISTOR SETTINGS
f_SW
(kHz)
296
R_SET
(kΩ)
14.7, or Connect to SGND
320
16.2
364
17.8
400
19.6
421
21.5, or OPEN
471
23.7
533
26.1
571
28.7
615
31.6, or Connect to V25
727
34.8
800
38.3
842
42.2
889
1067
46.4
51.1
Loop Compensation
The module loop response is programmable via the PMBus
command ASCR_CONFIG or by using the pin-strap method (ASCR
pin) according to Table 6. The ISL8273M uses the ChargeMode™
control algorithm that responds to the output current changes
within a single PWM switching cycle, achieving a smaller total
output voltage variation with less output capacitance than
traditional PWM controllers.
TABLE 6. ASCR RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
R_SET
(kΩ)
80
90
10
120
90
11, or Connect to SGND
160
90
12.1
200
90
13.3, or OPEN
240
90
14.7
280
90
16.2
Submit Document Feedback ₁₇
FN8704.2
March 16, 2016