ISL78020 Datasheet, PDF (17/19 Pages) Intersil Corporation – Automotive Grade TFT-LCD DC/DC with Integrated Amplifiers

ISL78020, ISL78022
Driving Capacitive Loads
ISL78020 and ISL78022 can drive a wide range of capacitive
loads. As load capacitance increases, however, the –3dB
bandwidth of the device will decrease and the peaking will
increase. The amplifiers drive 10pF loads in parallel with
10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of
peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5Ω and 50Ω) can be
placed in series with the output. However, this will obviously
reduce the gain. Another method of reducing peaking is to
add a “snubber” circuit at the output. A snubber is a shunt
load consisting of a resistor in series with a capacitor. Values
of 150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current and reduce the
gain.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point, the device will be latched off
until either the input supply voltage or enable is cycled.
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V_REF and V_DD bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R₁, R₁₁,
R₄₁) and the V_REF capacitor, C₂₂, the C_DELAY capacitor
C₇ and the integrator capacitor C₂₃.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
17
FN6386.2
December 6, 2007