ISL6730D_14 Datasheet, PDF (17/19 Pages) Intersil Corporation – Power Factor Correction Controllers

ISL6730A, ISL6730B, ISL6730C, ISL6730D
Gmv
2.5V
FB
VOUT
R_FB2
I_FB
R_FB1
COMP
Rvc
Cvp
Cvc
FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION
Thus, the transfer function from V_COMP to V_OUT is:
G_PS(s)=
-^V----^O----^U----^T----⁽---^s---⁾
Δ_COMP
=
-------¹--------
C_O ⋅ s
⋅
-^I--^D----⁽--^a----^v---^e---⁾-
Δ_COMP
G_PS(s)=
⎛
⎜
⎝
I_{--D-----(--a---v---e---)}
C_O ⋅ s
⋅
-_Δ---_C-----_O¹----_M-----_P--_{⎠⎟⎞}
=
-⁰---^.--⁵---⁹----⁸--
C_O ⋅ s
(EQ. 71)
(EQ. 72)
As shown in Figure 18, the voltage loop gain is:
G_VLOOP(s)= G_PS(s) • G_DIV • gmv • Z_COMP(s)
(EQ. 73)
The output feedback resistor divider gain, G_DIV is:
G_DIV=
-^V----^R----^E----^F--
V_OUT
(EQ. 74)
The compensation gain uses external impedance networks as
shown in Figure 18, Z_COMP(s) is given by:
Z_COMP(s)=
-------------------¹-------------------
(C_vc + C_vp) ⋅ s
•
---------^R----^v---^c----^•-----^C----^v---^c----^•-----^s----+-----¹----------
R_{-----v---c----}•_----C_{-----v---c----}•_----C_-----v---p-
C_vc + C_vp
•
s
+
1
(EQ. 75)
The targeted cross over frequency, F_CV is 8Hz. The high frequency
pole, F_Pv is required in order to reject the 2 time line frequency
component. F_Pv = 20Hz. The targeted phase margin is 60°.
100
F_Zv
80
F_CV
F_Pv
60
40
Gmv*Z_COMP(s)
G_PS(s)
20
0
G_VLOOP(s)
-20
-40
G_DIV
-60
1
10
100
1k
FREQUENCY (Hz)
FIGURE 19. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN
The zero, F_Zv is calculated:
F_Zv
=
----------------------------------^F----^C----^V-----------------------------------
tan (Φ_m + atan (F_CV ⁄ (F_Pv)))
F_Zv = -_t--_a---_n----₍--₆----₀----_d---_e----_g-----+-----_a----_t-_a-⁸---_n-^H---₍--^z₍--₈----_H-----_z---₎----_⁄--₍---₂---₀----_H-----_z---₎---₎---₎ = 1.15Hz
(EQ. 76)
(EQ. 77)
Then the total capacitance used for compensation is calculated:
C_vc + C_vp
=
--^G-----^P----^S----⁽--ⁱ---^•----⁽---²----^π---^F----^C----^V----⁾---⁾-----^•----^G-----^D----^I--^V-----^•----^G-----^m------^v-
(2πF_CV)
•
-⁽--^F----^C----^V-----^⁄---^F----^Z---^V----⁾--²-----+-----¹--
(F_CV ⁄ F_PV)² + 1
(EQ. 78)
Thus, the total compensation capacitance is:
C_vc + C_vp = 1829nF
C_vp
=
1829nF • -^F----^Z---^V--
F_PV
=
105 n F
C_vc = 1829nF – 105nF = 1724nF
(EQ. 79)
(EQ. 80)
(EQ. 81)
R_vc = ₂-----_â‹---_π-----_â‹---_F----_Z-¹---_V-----_â‹---_C----_V----_C-- = 81.2kΩ
(EQ. 82)
Choose components from the standard values. We have
C_VP = 100nF, C_VC = 1500nF, R_VC = 82.5kΩ. The actual bode plot
is shown in Figure 20.
60
40
20
0
0
-20
-40
90
75
60
45
30
15
0
1
10
100
FREQUENCY (Hz)
1x10³
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
17
FN8258.1
August 8, 2013