ISL65426 Datasheet, PDF (17/22 Pages) Intersil Corporation – 6A Dual Synchronous Buck Regulator with Integrated MOSFETs

ISL65426
enable level is defined in Equation 2. R1 is the resistor EN to
VCC2 and R2 is the resistor from EN to GND.
V_ENABLE
= R1 ⋅
0_----._--6_---V_{--- + 10μA}
R2
+ 0.6V
(EQ. 2)
Once the voltage at the EN pin reaches the enable
threshold, the 10μA current sink turns off.
With the part enabled and the current sink off, the disable
level is set by the resistor divider. The disable level is
defined in Equation 3.
V_DISABLE
=
0.6 V
⋅
R_-----1_-----+-----R_-----2_--
R2
(EQ. 3)
The difference between the enable and disable levels
provides the user with configurable hysteresis to prevent
nuisance tripping.
To enable the controller, the system enable must be high,
and one or both of the channel enables must be high. The
POR circuitry must be satisfied for both VCC and PVINx
inputs. Once these conditions are met, the controller
immediately initiates a power block configuration check.
ISL65426 EXTERNAL CONDITIONS
+VCC1
VCC
POR
LOGIC
SYSTEM ENABLE
COMPARATOR
EN
+
-
0.6V
10μA
+VCC2
R1
R2
FIGURE 37. SYSTEM ENABLE INPUT
Power Block Configuration Check
After VCC exceeds its POR rising threshold, the controller
decodes ISET1 and ISET2 states into one of four valid
power block configurations, see Table 1.These pins are not
checked again unless VCC falls below the POR falling
threshold. The valid configuration is saved for comparison
with the LX slave connectivity result determined during the
configuration check.
Once the POR and enable circuitry is satisfied, the controller
initiates a configuration check. The master power block of
output Channel 1 (Power Block 2) pulses high for 100ns.
The configuration check circuitry detects which power blocks
share a common LX connection and compare this to the
decoded valid configuration. The master power block of
output Channel 2 (Power Block 5) pulses and again the LX
pins of the other non-master blocks are monitored. The
common LX connections are checked versus the decoded
valid configuration. Each floating power block has a pull-
down active only during the configuration check to remove
noise related false positive detections.
A successful configuration check initiates a soft-start interval
100μs after completion. Failing the configuration check, the
controller will attempt a configuration check again 100μs
after completing the first check cycle. The controller repeats
the configuration check cycle every 100μs until a valid
configuration is detected or the controller is powered down.
Once successful, the configuration check is not implemented
again until VCC falls below the POR falling threshold.
Re-enabling the controller after a successful configuration
check will immediately initiate a soft-start interval.
Soft-start Interval
Once the controller is enabled and power block configuration
is successful, the digital soft-start function clamps the error
amplifier reference. The digital soft-start circuitry ramps the
output voltage by stepping the reference up gradually over a
fixed interval of 4ms. The controlled ramp of the output
voltage reduces the in-rush current during startup.
Power Good Signal
Each power good pin (PG1, PG2) is an open-drain logic
output which indicates when the converter output voltage is
within regulation limits. The power good pins pull low during
shutdown and remain low when the controller is enabled.
After a successful converter channel soft-start, the power
good pin signal associated with that channel releases and
the power good pin voltage rises with an external pull-up
resistor. The power good signal transitions low immediately
upon the removal of individual channel or system enable.
The power good circuitry monitors both output voltage FB
pins and compares them to the rising and falling limits shown
in the Electrical Specification Table. If either channel’s
feedback voltage exceeds the typical rising limit of 115% of
the reference voltage, the power good pin pulls low. The
power good pin continues to pull low until the feedback
voltage recovers down by a typical of 110% of the reference
voltage. If either channel’s feedback voltage drops below a
typical of 85% of the reference voltage, the power good pin
related to the offending channel(s) pulls low. The power
good pin continues to pull low until the feedback voltage
rises to within 90% of the reference voltage. The power good
pin then releases and signals the return of the output voltage
within the power good window.
Fault Monitoring and Protection
The ISL65426 actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the controller and external
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FN6340.1
November 14, 2006