ISL6251 Datasheet, PDF (17/20 Pages) Intersil Corporation – Low Cost Multi-Chemistry Battery Charger Controller

ISL6251, ISL6251A
The voltage gain with open current loop is:
T_v (S ) = KF_mF₁ (S)A_v (S)
Where
K = ^VFB
V_o
, V_FB is the feedback voltage of the voltage
error amplifier. The Voltage loop gain with current loop
closed is given by:
L_v
(
S
)
=
1
T_v (S)
+ T_i (S
)
If T_i(S)>>1, then it can be simplified as follows:
1+ ^S
L_v
(S
)
=
V_FB
V_o
R_o + R_L
R_T
ω _esr
1+ ^S
A_v (S)
H_e (S)
,
ω_p
≈
1
R_oC_o
ω_p
From the above equation, it is shown that the system is a
single order system, which has a single pole located at ^ω_p
before the half switching frequency. Therefore, simple type II
compensator can be easily used to stabilize the system.
Figure 15 shows the voltage loop compensator, and its
transfer function is expressed as follows:
iˆ_in
iˆ_L ^L
vˆ _o
vˆ _in
+
I_Ldˆ ^{1:D Vindˆ}
R_T
Rc
Ro
Co
T_i(S)
dˆ
K
Fm
+
He(S)
T_v(S)
vˆ_{comp -Av(S)}
FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS
BUCK REGULATOR
Vo
V_{FB -}
V_REF
g_m
+
V_COMP
R1
C1
FIGURE 15. VOLTAGE LOOP COMPENSATOR
w^Ah^v e^(Sre^{) =}ω^vˆ_c^vcˆ_zoFm=^Bp_R1^=1Cg₁
m
,
1
+^S
ω _cz
SC₁
Compensator design goal:
• High DC gain
•
Loop bandwidth f_c:
 ¹
⁵
−
1
20
 f_s

• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
1. Put compensator zero at:
ω_cz
=
(1 − 3) ¹
R_oC_o
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
ESR zero frequency or half switching frequency,
whichever is lower.
The loop gain T_v(S) at cross over frequency of f_c has unity
gain. Therefore, the compensator resistance R₁ is
determined by:
R₁
=
2π
f_cV_oC_o R_T
g _mV_FB
where g_m is the trans-conductance of the voltage loop error
amplifier. Compensator capacitor C1 is then given by:
C₁
=
1
R₁ ω_cz
Example: V_in=19V, V_o=16.8V, I_o=2.6A, f_s=300kHz,
C_o=10µF/10mΩ, L=10µH, g_m=250µs, R_T=0.2Ω, V_FB=2.1V,
V_PWM=V_IN/11, f_c=20kHz, then compensator resistance
R₁=8.0kΩ. Choose R₁=10kΩ. Put the compensator zero at
1.5kHz. The compensator capacitor is C₁=10nF. Therefore,
choose voltage loop compensator: R₁=10K, C₁=10nF.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
17
FN9202.1
June 17, 2005