ISL28134_14 Datasheet, PDF (17/25 Pages) Intersil Corporation – 5V Ultra Low Noise, Zero Drift Rail-to-Rail Precis Op Amp

V1
1e-6
2
R1
7.5004
R2
7.5004
Vin+
R21
En
IN+
1
En
VOS
0.2E-6
80
28
R22
EOS
5e11
+
+
-_-
D13
3
4
M14
NCHANNELMOSFET
M15
NCHANNELMOSFET
5
6
IN-
0
Vin-
V9
0
29
R23
5e11
Vcm
CinDif
4.71e-12
0.14
IOS
240e-12
R3
7 ^R4
10
10
Cin2
10.1e-12
Cin1
10.1e-12
I1
5e-3
I2
5e-3
8 ^R5
R6
10
10
9
10
PMOSISIL
M10
M11
PMOSISIL
11
12
R7
7.5
R8
13
7.5
V2
1e-6
G1A
+
-
GAIN = 233.426
RA1
1
D1
R9
14
100
D2
R10
1e9
15
G1
+
-
GAIN = 113.96e-3
R11
1
0.607
D3
17
V3
16
G2A
RA2
1
GAIN = 233.426
0.607
V4
G2
R12
1
GAIN = 113.96e-3
18
D4
Voltage Noise Stage
V+
Input Stage
E2
+
+
-_-
GAIN = 1
Differential to Single Ended
Conversion Stage
1st Gain Stage
D5
G3
+
-
GAIN = 68.225E-3
0.607
19
V5
C2
3.33E-09
R13
7346.06E6
G5
+
-
GAIN = 177.83E-6
Vg
Vmid
E4
+
0.607
V6
+
-^-
G4
GAIN = 68.225E-3
20
D6
R14
7346.06E6
C3
3.33E-09
G6
GAIN = 177.83E-6
V++
L1
7.957E-07
21
R15
1.00E-03
Vc
0
G7
+
-
GAIN = 879.62E-6
ISY
675E-6
R16
1.00E-03
22
L2
7.957E-07
G8
GAIN = 879.62E-6
R17
1136.85
C4
10e-12
23
R18
1136.85
C5
10e-12
G11
D9
D10
GAIN = 20e-3
D7
DX
24
V7
1.04
26
27
D8
25
V8
1.04
G10
G9
+
+
-
D12
D11
-
GAIN = 20e-3
GAIN = 20e-3
G12
GAIN = 20e-3
2nd Gain Stage
Mid Supply ref V
Common Mode
Gain Stage
with Zero
V--
E3
+
V-
+
-^-
GAIN = 1
2nd Pole Stage
0
Supply Isolation
Stage
FIGURE 48. SPICE SCHEMATIC
Output Stage
R19
50
VOUT
R20
50