HIP2103 Datasheet, PDF (17/21 Pages) Intersil Corporation – 60V, 1A/2A Peak, 1/2 Bridge Driver with 4V UVLO

HIP2103, HIP2104
The negative transient on the HS pin is the result of the parasitic
inductance of the low-side drain-source conductor path on the
PCB. Even the parasitic inductance of the low-side FET body
contributes to this transient. When the high-side bridge FET turns
off (see Figure 24), as a consequence of the inductive
characteristics of a motor load, the current that was flowing in
the high-side FET (blue) must rapidly commutate through the low
side FET (red). The amplitude of the negative transient impressed
on the HS node is (L x di/dt) where L is the total parasitic
inductance of the low-side FET drain-source path and di/dt is the
rate at which the high-side FET is turned off. With the increasing
current levels of new generation motor drives, appropriately
clamping of this transient becomes more significant for the
proper operation of bridge drivers. Fortunately, the HIP2103,
HIP2104 can withstand greater amplitudes of negative
transients than what is available in many other bridge drivers.
The maximum negative voltage on the HS pin is rated for -10V
with no time during limit.
Another component of negative voltage is from the body diode of
the low side FET during the dead time. When current is flowing
from source to drain, the conduction voltage is approximately
1 to 1.5V negative impressed on the HS pin (possibly greater
during fault load conditions). Because the HIP2103, HIP2104 is
rated for -10V without any time constraints, this negative voltage
component is of no consequence.
HB
HO
C_BOOT
HS
-
+
Inductive
Load
LO
-
VSS
+
FIGURE 24. PARASITIC INDUCTANCE ON HS NODE
In the unlikely event that the negative transient exceeds -10V,
there are several ways of reducing the negative amplitude of this
transient if necessary. If the bridge FETs are turned off more
slowly to reduce di/dt, the amplitude will be reduced but at the
expense of more switching losses in the FETs. Careful PCB design
will also reduce the value of the parasitic inductance. However, in
extreme cases, these two solutions by themselves may not be
sufficient. Figure 25 illustrates a simple method for clamping the
negative transient. Two series connected, fast 1 amp PN junction
diodes are connected between HS and VSS as shown. It is
important that these diodes be placed as close as possible to the
HS and VSS pins to minimize the parasitic inductance of this
current path between the two pins. Two diodes in series are
required because they are in parallel with the body diode of the
low side FET. If only one diode is used for the clamp, it will
conduct some of the negative load current that is flowing in the
body diode of the low side FET.
HB
HO
CBOOT
HS
LO
VSS
Inductive
Load
-
1V
+
FIGURE 25. TWO CLAMPING DIODES TO SUPPRESS NEGATIVE
TRANSIENTS
An alternative to the two series connected diodes is one diode
and a resistor (Figure 26). In this case, it is necessary to limit the
current in the diode with a small value resistor, R_HS, connected
between the phase node of the 1/2 bridge and the HS pin.
Observe that R_HS is effectively in series with the HO output and
serves as a peak current limiting gate resistor on HO.
HB
HO
C_BOOT
R_HS
HS
-
+
Inductive
Load
LO
-
VSS
+
FIGURE 26. RESISTOR AND DIODE NEGATIVE TRANSIENT CLAMP
The value of R_HS is determined by how much average current in
the clamping diode is acceptable. Current in the low side FET
flows through the body diode during the dead time resulting with
a negative voltage on HS that is typically about -1.5V. When the
low-side FET is turned on, the current through the body diode is
shunted away into the channel and the conduction voltage from
source to drain is typically much less than the conduction voltage
through the body diode. Consequently, significant current will
flow in the clamping diode only during the dead time. Because
the dead time is much less than the on time of the low side FET,
the resulting average current in the clamping diode is very low.
The value of R_HS is then chosen to limit the peak current in the
clamping diode and usually just a few ohms is necessary.
The methods to clamp the negative transients with diodes can
still result with high frequency oscillations on the HS node
depending on the parasitics of the PCB design. An alternative to
the clamping diode in Figure 26 is a small value capacitor
instead of the diode. This capacitor and R_HS is very effective for
minimizing the negative spike amplitude and oscillations.
17
FN8276.0
November 27, 2013