X4323 Datasheet, PDF (16/21 Pages) Intersil Corporation – CPU Supervisor with 32K EEPROM

TIMING DIAGRAMS
Bus Timing
SCL
t_SU:STA
SDA IN
t_F
t_HD:STA
X4323, X4325
t_HIGH
t_LOW
t_SU:DAT
t_HD:DAT
SDA OUT
t_R
t_AA t_DH
t_SU:STO
t_BUF
WP Pin Timing
SCL
SDA IN
WP
START
Clk 1
Slave Address Byte
Clk 9
t_SU:WP
t_HD:WP
Write Cycle Timing
SCL
SDA
8th bit of Last Byte
ACK
Stop
Condition
t_WC
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
t_WC(1)
Parameter
Write Cycle Time
Min.
Typ.⁽¹⁾
5
Max.
10
Unit
ms
Notes: (1) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
16
FN8122.0
March 29, 2005