KAD5612P_0909 Datasheet, PDF (16/29 Pages) Intersil Corporation – Dual 12-Bit, 250/210/170/125MSPS A/D Converter

KAD5612P
1.8
1.4
INP
1.0
0.725V
0.6
0.2
INN
VCM
0.535V
FIGURE 26. ANALOG INPUT RANGE
An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
schemes are shown in Figures 27 and 28.
ADT1-1WT
ADT1-1WT
1000pF
KAD5612P
VCM
0.1µF
FIGURE 27. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADTL1-12 ADTL1-12
1000pF
1000pF
0.1µF
KAD5612P
VCM
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5612P is 1000Ω.
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
69.8OΩ
100OΩ
0.22µF
49.9OΩ
100OΩ
69.8OΩ
348OΩ
CM
348OΩ
25OΩ
217OΩ
25OΩ
0.1µF
KAD5612P
VCM
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in Figure 29, can be used in
applications that require dc-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8V_P-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
TC4-1W
200pF
CLKP
200pF
1000pF
200OΩ
200pF
CLKN
FIGURE 30. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 19.
16
FN6803.2
September 9, 2009