ISL6185_11 Datasheet, PDF (16/20 Pages) Intersil Corporation – Dual USB Port Power Supply Controller 2.5V to 5V Operating Range

ISL6185
Application Information
Using the ISL6185xEVAL1Z Platform
General and Biasing Information
There are three evaluation platforms for the ISL6185 family.
There is one platform for each package style, each with a
different continuous output current level and a mix of enable
polarity and output retry or latch options. See page 4, at the end
of the “Ordering Information” table, for information on the
standard available evaluation board options. Figure 32A shows
the common schematic for all three evaluation boards. See “Pin
Configurations” on page 5 for details and differences.
The evaluation platform is biased and monitored through
numerous labeled test points. See Table 1 for test point
assignments and descriptions.
TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS
TP NAME
DESCRIPTION
GND
Eval Board and IC Gnd
V+
Eval Board and IC Bias
EN1
Enable Switch 1
EN2
Enable Switch 2
FLT2
Switch 2 Fault
OUT2
Switch Out 2
OUT1
Switch Out 1
FLT1
Switch 1 Fault
Upon proper bias of the evaluation platform and correct enabling
of the IC, the ISL6185 will have a nominal V_IN/10Ω load current
that is lower than the continuous current rating passing through
each enabled switch. See Figures 13 and 14 for typical ISL6185
turn-on and turn-off waveforms.
External current loading in excess of the trip current level for the
particular part being evaluated will result in the ISL6185 entering
the current limiting mode. Figure 16 illustrates the current
limiting mode for the ISL6185 product variants with 0.6A of
continuous load current rating. The scope shot shows current
limiting for ~12ms before it is turned off and the fault signal is
asserted.
Application Considerations
The application considerations for the ISL6185 family are widely
accepted best industry practices. Good decoupling practices on
the VIN pin must be followed: placement close to the IC, with at
least 2.2µF recommended. It is recommended to reduce the
input and output inductance to the ISL6185 with good PCB
layout practices.
When designing with the 1.5A and 1.8A versions in an
implementation in which the output may be unloaded (open)
while the ISL6185 is turned on, a minimum of 4.7µF of
capacitive output load is recommended to prevent high dv/dt
from unnecessarily activating the surge/ESD control circuit.
The ISL6185 provides several continuous current rated devices
specified at V_IN = 5V; these are 0.6A, 1.1A, 1.5A and 1.8A
options that are capable over the entire temperature extreme. At
V_IN = 3.3V, the current capability is degraded, and the ISL6185 is
specified at 0.6A, 1.1A, 1.3A and 1.5A, respectively. At
V_IN = 2.5V, there are no minimum specifications, but a typical
value is provided for +25°C operation (see “Electrical
Specifications” on page 6). This degraded capability is due to the
higher r_DS(ON) of the FET switch at the lower bias voltage.
The enhanced thermal characteristics and increased number of
bond wires allow the 10 Ld DFN to have a higher current
capability than either the 8 Ld SOIC or the DFN.
TABLE 2. ISL6185XEVAL1Z BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT
FUNCTION
COMPONENT DESCRIPTION
U1
ISL6185
Intersil, ISL6185
R3 - R4
Output Load
Resistors
10Ω, 5%, 3W
R1 - R2
FLT Output Pull-up 10kΩ, 0805
Resistor
C1
Decoupling
2.2µF, 0805
Capacitor
C2 - C3
Load Capacitor
10µF 16V Electrolytic,
Radial Lead
16
FN6937.1
June 27, 2011