ISL59530 Datasheet, PDF (16/22 Pages) Intersil Corporation – 16x16 Video Crosspoint

Block Diagram
VREF
-
+
2uA
ISL59530
VS+ VOVERn OVERn
16
OVERLAY
INPUT
16
LOGIC
CONTROL
16 INPUTS
Power-on
Clamp
Enable
SWITCH
MATRIX
16 OUTPUTS
SDI
SCLK
SLATCH
-
+
2uA
Av Output
x1, x2 Enable
Power-on
SPI INTERFACE, REGISTER
SDO
General Description
The ISL59530 is a 16x16 integrated video crosspoint switch
matrix with input and output buffers and On-Screen Display
(OSD) insertion. This device operates from a single +5V
supply. Any output can be generated from any of the 16 input
video signal sources, and each output can have OSD
information inserted through a dedicated, fast 2:1 mux
located before the output buffer. There is also a Broadcast
mode allowing any one input to be broadcast to all 16
outputs. A DC restore clamp function enables the ISL59530
to AC-couple incoming video.
The ISL59530 offers a -3dB signal bandwidth of 300MHz.
Differential gain and differential phase of 0.025% and 0.05°
respectively, along with 0.1dB flatness out to 50MHz make
this ideal for multiplexing composite NTSC and PAL signals.
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible, three-wire
serial interface. The ISL59530 interface is designed to
facilitate both fast initialization and configuration changes.
On power-up, all outputs are initialized to the disabled state
to avoid output conflicts in the user’s system.
Digital Interface
The ISL59530 uses a serial interface to program the
configuration registers. The serial interface uses three
signals (SCLK, SDI, and SLATCH) for programming the
ISL59530, while a fourth signal (SDO) enables optional
daisy-chaining of multiple devices. The serial clock can run
at up to 5MHz (5Mbits/s).
Serial Interface
The ISL59530 is programmed through a simple serial
interface. Data on the SDI (serial data input) pin is shifted
into a 16-bit shift register on the rising edge of the SCLK
(serial clock) signal. (This is continuously done regardless of
the state of the SLATCH signal.) The LSB (bit 0) is loaded
first and the MSB (bit 15) is loaded last (see the Serial
Timing Diagram). After all 16 bits of data have been loaded
into the shift register, the rising edge of SLATCH updates the
internal registers.
While the ISL59530 has an SDO (Serial Data Out) pin, it
does not have a register readback feature. The data on the
SDO pin is an exact replica of the incoming data on the SDI
pin, delayed by 15.5 SCLKs (an input bit is latched on the
rising edge of SLCK, and is output on SDO on the falling
edge of SLCK 15.5 SCLKs later). Multiple ISL59530’s can be
daisy-chained by connecting the SDO of one to the SDI of
the other, with SCLK and SLATCH common to all the daisy-
chained parts. After all the serial data is transmitted (16 bits *
n devices = 16*n SCLKs), the rising edge of SLATCH will
update the configuration registers of all n devices
simultaneously.
The Serial Timing Diagram and Serial Timing Parameters
table show the timing requirements for the serial interface.
16
FN6220.1
June 12, 2006