ISL23425_15 Datasheet, PDF (16/20 Pages) Intersil Corporation – Dual, 256-Tap, Low Voltage Digitally Contro Potentiometer (XDCP™)

ISL23425
Applications Information
Communicating with ISL23425
Communication with ISL23425 proceeds using SPI interface
through the ACR (address 10000b), WR0 (addresses 00000b)
and WR1 (addresses 00001b) registers.
The wiper of the potentiometer is controlled by the WRi register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Configuration
When an application needs more than one ISL23425, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown in Figure 29. In Daisy Chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note, the number of daisy chained DCPs is
limited only by the driving capabilities of the SCK and CS pins of
the microcontroller; for larger number of SPI devices buffering of
SCK and CS lines is required.
Daisy Chain Write Operation
The write operation starts by HIGH-to-LOW transition on CS line,
followed by N number of two bytes write instructions on SDI line
with reversed chain access sequence: the instruction byte + data
byte for the last DCP in chain is going first, as shown in Figure 30,
where N is a number of DCPs in chain. The serial data is going
through DCPs from DCP0 to DCP(N-1) as follow: DCP0 --> DCP1 -->
DCP2 --> ... --> DCP(N-1). The write instruction is executed on the
rising edge of CS for all N DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists of two parts: first, send the read
instructions (N two bytes operation) with valid address; second,
read the requested data while sending NOP instructions (N two
bytes operation) as shown in Figures 31 and 32.
The first part starts by HIGH-to-LOW transition on CS line,
followed by N two bytes read instruction on SDI line with reversed
chain access sequence: the instruction byte + dummy data byte
for the last DCP in chain is going first, followed by LOW-to-HIGH
transition on CS line. The read instructions are executed during
the second part of read sequence. It also starts by HIGH-to-LOW
transition on CS line, followed by N number of two bytes NOP
instructions on SDI line and LOW-to-HIGH transition of CS. The
data is read on every even byte during the second part of the
read sequence while every odd byte contains code 111b followed
by address from which the data is being read.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients,
but that will also reduce the useful bandwidth of the circuit, thus
may not be a good solution for some applications. It may be a
good idea, in that case, to use fast amplifiers in a signal chain for
fast recovery.
V_LOGIC Requirements
It is recommended to keep V_LOGIC powered all the time during
normal operation. In a case where turning V_LOGIC OFF is
necessary, it is recommended to ground the V_LOGIC pin of the
ISL23425. Grounding the V_LOGIC pin or both V_LOGIC and V_CC does
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
the V_LOGIC pin.
V_CC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V_CC pin.
CS
SCK
MOSI
MISO
µC
DCP0
CS
SCK
SDI
SDO
N DCP IN A CHAIN
DCP1
CS
SCK
SDI
SDO
DCP2
CS
SCK
SDI
SDO
DCP(N-1)
CS
SCK
SDI
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
16
FN7873.1
September 11, 2015