ISL1591_14 Datasheet, PDF (16/18 Pages) Intersil Corporation – Fixed Gain, Dual Port, VDSL2 Line Driver

ISL1591
Power Control Function
+VCC IBIAS IBIAS +VCC
+3.3V
+3.3V
+VCC IBIAS IBIAS +VCC
+3.3V
+3.3V
50kΩ
50kΩ50kΩ
50kΩ
CO
+1.4V
C1 CO
+1.4V
C1
+1V
50kΩ
FIGURE 50. BIAS CONTROL CIRCUIT
C0_AB and C1_AB control the quiescent current for the port
constructed from amplifiers A and B. If both control lines are
unconnected externally, the internal 50kΩ pull-up will switch the
differential pairs to divert the 100µA tail currents into the supply
turning off the amplifiers. Taking both control pins low will pass
both I_BIAS lines on into scaling current sources. When C₀ and C₁
are low, the typical 14mA total quiescent current for a port is
shown in the “Electrical Specification” tables on page 4. Taking
C₀ high (>2V) while leaving C₁ low (<0.8V) will reduce the current
into a port to a typical 9.7mA. Taking C₁ high, while leaving C₀
low will reduce the current in a port to a typical 7.4mA supply
current. Table 2 summarizes the operation modes for ISL1591
for each port.
TABLE 2. POWER MODES OF THE ISL1591
C₁
C₀
OPERATION
0
0
I_S Full Power Mode
0
1
I_S Medium Power Mode
1
0
I_S Low Power Mode
1
1
Power-Down
Performance Considerations
Driving Capacitive Loads
All closed loop op amps are susceptible to reduced phase margin
when driving capacitive loads. This shows up as peaking in the
frequency response that can, in extreme situations, lead to
oscillations. The ISL1591 is designed to operate successfully
with small capacitive loads such as layout parasitics. As the
parasitic capacitance increases, it is best consider a small
resistor in series with the output to isolate the phase margin
effects of the capacitor. Figure 23 on page 9 shows the effect of
capacitive load. With 22pF on each output, we see about 6dB
peaking. This will increase quickly at higher C_LOADS.
Output Headroom Model
Driving high voltages into heavy loads will require a careful
consideration of the available output swing vs. load. Figure 51
shows a useful model for predicting the available output swing. If
the output is modeled as ideal NPN and PNP transistors, the
output swing limits can be described as no load headrooms (V_P
and V_N) and an equivalent impedance to the supplies (R_P and
R_N).
+VS
RP
VP
+
–
±VO
RL
VN
+
–
RN
GND
FIGURE 51. HEADROOM MODEL
The no load headrooms can be found in the “Electrical
Specifications” table on page 5 as 24V - 22.4V = 1.6V giving 0.8V
to each supply.
The equivalent impedances for this model can be extracted from
the reduced swings shown in the specification table for the 100Ω
load. Looking at the typical 100Ω load swings, we see a +21.2V
swing. Solving for the two resistors in the Headroom model
shown in Figure 51 gives Equation 7:
R_p = 2.8Ω and R_n = 2.8Ω
(EQ. 7)
For the differential configuration, Figure 52 shows the Headroom
model that can be used to predict the maximum available swing
for a given supply voltage and load resistor, R_L.
+VS
-
+
VP
RL
-
+
GND
FIGURE 52. HEADROOM MODEL
For equal bipolar supplies, the available peak output swing will
be given by Equation 8:
V_p
=
2(V_s
1+
−V_p −V_n )
R_p + R_n
R_L
(EQ. 8)
For example, to worst case the design using +24V supplies with
±5% supply tolerance and a minimum expected load of 50Ω, a
maximum V_P can be calculated as shown in Equation 9:
V_peak
=
(V_s −V_p −V_n )
1+ ^{Rp + Rn}
R_L
=
(22.8 −1.6)
1+ ^{2.8Ω + 2.8Ω}
50Ω
= 19.1V_peak
(EQ.
9)
16
FN7625.1
October 31, 2012