HC5515_06 Datasheet, PDF (16/20 Pages) Intersil Corporation – ITU CO/PABX SLIC with Low Power Standby

HC5515
3.4kHz and compare to 1kHz reading.
V_TR and E_RX are defined in Figure 9.
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
to 4-wire frequency response is measured with respect to
E_RX = 0dBm at 1.0kHz, E_G = 0V, I_DCMET = 23mA. The
frequency response is computed using the following equation:
F_4-4 = 20 • log (V_TX/E_RX), vary frequency from 300Hz to
3.4kHz and compare to 1kHz reading.
V_TX and E_RX are defined in Figure 9.
19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire
insertion loss is measured with respect to E_G = 0dBm at 1.0kHz
input signal, E_RX = 0, I_DCMET = 23mA and is computed using
the following equation:
L_2-4 = 20 • log (V_TX/V_TR)
where: V_TX, V_TR, and E_G are defined in Figure 9. (Note: The
fuse resistors, R_F , impact the insertion loss. The specified
insertion loss is for R_F = 0).
20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E_RX = 0dBm, 1.0kHz
input signal, E_G = 0, I_DCMET = 23mA and is computed using
the following equation:
L_4-2 = 20 • log (V_TR/E_RX),
where: V_TR and E_RX are defined in Figure 9.
21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
gain tracking is referenced to measurements taken for
E_G = -10dBm, 1.0kHz signal, E_RX = 0, I_DCMET = 23mA and is
computed using the following equation.
G_2-4 = 20 • log (V_TX/V_TR) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V_TX and V_TR are defined in Figure 9.
22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
gain tracking is referenced to measurements taken for
Pin Descriptions
E_RX = -10dBm, 1.0kHz signal, E_G = 0, I_DCMET = 23mA and is
computed using the following equation:
G_4-2 = 20 • log (V_TR/E_RX) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V_TR and E_RX are defined in Figure 9. The level is specified at
the 4-wire receive port and referenced to a 600Ω impedance
level.
23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
at V_TR is specified with the 2-wire port terminated in 600Ω (R_L)
and with the 4-wire receive port grounded (Reference Figure 10).
24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
at V_TX is specified with the 2-wire port terminated in 600Ω (R_L).
The noise specification is with respect to a 600Ω impedance
level at V_TX. The 4-wire receive port is grounded (Reference
Figure 10).
25. Harmonic Distortion (2-Wire to 4-Wire) - The
harmonic
distortion is measured with the following conditions.
E_G = 0dBm at 1kHz, I_DCMET = 23mA. Measurement taken at
V_TX. (Reference Figure 7).
26. Harmonic Distortion (4-Wire to 2-Wire) - The
harmonic
distortion is measured with the following conditions. E_RX =
0dBm0. Vary frequency between 300Hz and 3.4kHz, I_DCMET =
23mA. Measurement taken at V_TR. (Reference Figure 9).
27. Constant Loop Current - The constant loop current is
calculated using the following equation:
I_L = 2500 / (R_DC1 + R_DC2).
28. Standby State Loop Current - The standby state loop current
is calculated using the following equation:
I_L = [|V_BAT| - 3] / [R_L +1800], T_A = 25°C.
29. Power Supply Rejection Ratio - Inject a 100mV_RMS signal
(50Hz to 4kHz) on V_BAT, V_CC and V_EE supplies. PSRR is
computed using the following equation:
PSRR = 20 • log (V_TX/V_IN). V_TX and V_IN are defined in Figure 11.
PLCC SYMBOL
DESCRIPTION
1
RING_SENSE Internally connected to output of RING power amplifier.
2
BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
V_CC
+5V power supply.
5
RINGRLY Ring relay driver output.
6
V_BAT
Battery supply voltage, -24V to -56V.
7
R_SG
Saturation guard programming resistor pin.
8
NC
This pin is used during manufacturing. This pin is to be left open for proper SLIC operation.
9
E0
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to
a logic level one.
11
DET
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is
an open collector with an internal pull-up of approximately 15kΩ to V_CC.
12
C2
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
16
FN4235.6
June 6, 2006