ISL9492_14 Datasheet, PDF (15/21 Pages) Intersil Corporation – Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Satellite Set-Top Box Designs

ISL9492
capacitor with an inductor of 15µH can cause a peak inductor
current of approximately 1A.
Output Voltage Selection
The device offers a flexible means to select the output voltage.
When VSPEN is LOW, the output voltage can be selected by the
SVTOP pin. In this case, when the SVTOP pin is LOW, the output
voltage is either 13V or 14V, depending on the VBOT bit. When
the SVTOP pin is HIGH, the output voltage is either 18V or 20V
depending on the VTOP bit. When VSPEN is HIGH, the SVTOP pin
is ignored, and the output is selected by both the VTOP and the
VBOT bits. See Table 1.
VSPEN
0
0
0
0
1
1
1
1
VTOP
X
X
0
1
0
0
1
1
TABLE 1.
VBOT
0
1
X
X
0
1
0
1
SVTOP
0
0
1
1
X
X
X
X
VOUT
13.5V
14.2V
18.5V
20V
13.5V
14.2V
18.5V
20V
Current Limiting
Both the boost converter and the linear regulator have
independent current limit. In the boost converter, this is achieved
through cycle-by-cycle internal current limit. In the linear
regulator, current limit threshold is set by the ISELH and ISELL
bits (see Table 9). At any time, when the linear regulator goes
into current limit and the DCL bit is high, the OLF bit is set. OLF
bit is not affected by current limit occurred through the boost
converter. In this mode, the part will deliver the full specified
current for 50ms. During this time, if the current limit condition
disappears, the OLF bit will be cleared and the part restarts. If
the part is still in current limit after this time period, the linear
regulator and boost converter will automatically disable for
900ms to prevent the part from overheating. After this shutdown
period, the ISL9492 will automatically re-enable itself and the
above described sequence will repeat. This current limit method
is also called “Dynamic current limit”. The ISL9492 can also be
configured so when a current limit is detected, the part rather
than disabling the linear regulator after 50ms stays powered up
and delivers the programmed load current in a constant current
mode. This mode can be enabled by writing a “0” in the DCL bit.
In this mode, the OLF bit is set high to indicate an overcurrent
condition. This current limiting method is also called “Static
Current Limit”. This method can be used to enable any loads
which are highly capacitive during start-up.
Thermal Protection and Fault Indicator
When the junction temperature reaches the critical temperature,
the boost converter and the linear regulator are immediately
disabled with the OTF bit set. Only when the junction temperature
cools down to a lower temperature threshold specified will this
bit will be cleared and the part be allowed to restart.
When any of the fault handling flags (OTF, CABF, OUVF, OLF, BCF)
are set, the fault indicator pin FLT will go LOW. This status output
can serve as an interrupt signal to a microcontroller. The OUVF bit
will be low indicating the output voltage is good and within 90%
of final steady-state DC value, so during output voltage
transitions, this bit will go high indicating output voltage is out of
regulation followed by going low; see Figure 4. This bit can be
used as an output for the system to know that the LNB output
voltage is in regulation and it can start communicating with the
LNB by transmitting the 22kHz tone. The system will be able to
apply internal or external tone only after the OUVF bit is pulled
low and during tone application, the bit will stay latched low. BCF
bit is set when back bias is detected; OLF bit is set when an
overcurrent is detected; CABF bit is set low when there is
maximum of 50mA of load current; OTF bit is set when the die
junction temperature reaches +150°C; all these registers are
activated after the LDO is enabled by the DLIN bit in SR4 register.
22kHz TONE
22kHz TONE ^±12%
±12%
VLNB
OUVF BIT
VSPEN/SVTOP
DLIN BIT
FIGURE 26. OUTPUT POWER SEQUENCE
I²C Bus Interface for ISL9492
(Refer to Philips I²C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL9492 and
vice versa takes place through the two-wire I²C bus interface,
consisting of the two lines SDA and SCL. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage via a pull-
up resistor. (Pull-up resistors to positive supply voltage must be
externally connected). When the bus is free, both lines are HIGH. The
output stages of ISL9492 will have an open drain/open collector in
order to perform the wired-AND function. Data on the I²C bus can be
transferred up to 100kbps in the standard-mode or up to 400kbps
in the fast-mode. The level of logic “0” and logic “1” is defined in the
“Electrical Specifications” table on page 8. One clock pulse is
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH period of
the clock. The HIGH or LOW state of the data line can only change
when the clock signal on the SCL line is LOW. Refer to Figure 27.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 27. DATA VALIDITY
15
FN6547.1
March 17, 2011