ISL854102 Datasheet, PDF (15/19 Pages) Intersil Corporation – Wide VIN 1.2A Synchronous Buck Regulator

ISL854102
The inductor current rating should be such that it will not saturate
in overcurrent conditions. For typical ISL854102 applications,
inductor values generally lie in the 10µH to 47µH range. In
general, higher V_OUT will mean higher inductance.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors may also be
used.
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturers datasheet to
determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, however, an assumption of ~20% further
reduction will generally suffice. The result of these
considerations may mean an effective capacitance 50% lower
than nominal and this value should be used in all design
calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
V_OUTripple=
----------------^----^I----------------
8^ f_{S W}^ C_{O U T}
(EQ. 6)
Where I is the inductor’s peak-to-peak ripple current, f_SW is the
switching frequency and C_OUT is the output capacitor.
If using electrolytic capacitors then:
V_OUTripple= I*ESR
(EQ. 7)
Loop Compensation Design
When COMP is not connected to VCC, the COMP pin is active for
external loop compensation. The ISL854102 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing pilot
device in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant,
and the system becomes a single order system. It is much easier
to design a Type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 36 shows the small signal model of the
synchronous buck regulator.
^iin
V^in
+
ILd^ 1:D ^{Vind^}
^iL _LP
R_LP
R_T
vo^
Rc
Ro
Co
d^
Ti(S)
K
Fm
+
He(S)
Tv(S)
V^{^}_{comp -Av(S)}
FIGURE 36. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R₂
C₃
V_FB
-
V_COMP
V_REF
GM
R₃
+
R₆
C₇
C₆
FIGURE 37. TYPE II COMPENSATOR
Figure 37 shows the type II compensator and its transfer function
is expressed as shown in Equation 8:
A_vS= ^v-ˆ---^C-_v-ˆ--^O-_F---_BM-----^P-- = -_--_C-----₆----+-----_C-^G---₇--^M--_---_--^-_--^R-_R---³-₂-----+-----_R----₃----_ -_S--^--_-¹--₁---+--+---^----_{--------}^cS------_cS---^z------_p---¹-----₁--^--_-^--_-¹--₁---+--+---^-----_{-------}^c-^S-----_c--_S-^z------_p---²------₂^_{----}-
(EQ. 8)
Where,
_cz1 = -_R----₆--¹-_C-----₆- , _cz2 = -_R----₂--¹-_C-----₃- _cp1= _R--^C---₆-⁶---_C--+--₆--^C-_C----⁷-₇- _cp2= _C--^R---₃-²--_R---+--₂--^R-_R----³-₃-
Compensator design goal:
High DC gain
Choose loop bandwidth f_c less than 100kHz
Gain margin: >10dB
Phase margin: >40°
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FN8870.0
July 1, 2016