ISL8022 Datasheet, PDF (15/18 Pages) Intersil Corporation – Dual 2A/1.7A Low Quiescent Current 2.25MHz High Efficiency Synchronous

ISL8022
PWM
PFM
CLOCK
I_L
0
V_OUT
16 CYCLES
PFM CURRENT LIMIT
NOMINAL +1.5%
NOMINAL
FIGURE 44. SKIP MODE OPERATION WAVEFORMS
LOAD CURRENT
Positive and Negative Overcurrent
Protection
CSA1 and CSA2 are used to monitor output 1 and
output 2 channels respectively. The overcurrent
protection is realized by monitoring the CSA_ output with
the OCP threshold logic, as shown in the “Block Diagram”
on page 3. The current sensing circuit has a gain of
0.32V/A, from the P-MOSFET current to the CSA_ output.
When the CSA_ output reaches the threshold of 1.25V
for Channel 1 and 1.1V for Channel 2, the OCP
comparator is tripped to turn off the P-MOSFET
immediately. The overcurrent function protects the
switching converter from a shorted output by
monitoring the current flowing through the upper
MOSFETs.
Upon detection of an overcurrent condition, the upper
MOSFET will be immediately turned off and will not be
turned on again until the next switching cycle. Upon
detection of the initial overcurrent condition, the
Overcurrent Fault Counter is set to 1 and the Overcurrent
Condition Flag is set from LOW to HIGH. If, on the
subsequent cycle, another overcurrent condition is
detected, the OC Fault Counter will be incremented. If
there are seventeen sequential OC fault detections, the
regulator will be shut down under an Overcurrent Fault
Condition. An Overcurrent Fault Condition will result with
the regulator attempting to restart in a hiccup mode with
the delay between restarts being 4 soft-start periods. At
the end of the fourth soft-start wait period, the fault
counters are reset and soft-start is attempted again. If
the overcurrent condition goes away prior to the OC Fault
Counter reaching a count of four, the Overcurrent
Condition Flag will set back to LOW.
In the event that the inductor current reaches -1.6A, the
part enters Negative Overcurrent Protection. At this
point, all switching stops and the part enters tri-state
mode while the pull-down FET is discharging the output
until it reaches normal regulation voltage, then the IC
restarts switching.
PG
The power-good signal (PG), monitors both of the output
channels. When powering up, the open-collector
Power-On-Reset output holds low for about 1ms after
V_O1 and V_O2 reaches the preset voltages. The PG output
also serves as a 1ms delayed power-good signal. If one
of the outputs is disabled, then PG only monitors the
active channels. There is an internal 1MΩ pull-up resistor.
UVLO
When the input voltage is below the undervoltage
lock-out (UVLO) threshold, the regulator is disabled.
Enable
The enable (EN1, EN2) input allows the user to control
the turning on or off the regulator for purposes such as
power-up sequencing. The regulator is enabled, there is
typically a 600µs delay for waking up the bandgap
reference and the soft start-up begins.
Soft Start-Up
The soft start-up eliminates the inrush current during the
start-up. The soft-start block outputs a ramp reference to
both the voltage loop and the current loop. The two
ramps limit the inductor current rising speed as well as
the output voltage speed so that the output voltage rises
in a controlled fashion. At the very beginning of the
start-up, the output voltage is less than 0.2V; hence the
PWM operating frequency is 1/3 of the normal frequency.
In forced PWM mode, the IC will continue to start-up in
PFM mode to support pre-biased load applications.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, or the
output undervoltage fault latch is set, the outputs
discharge to GND through an internal 100Ω switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency.
The ON-resistance for the P-MOSFET is typically 100mΩ
and the ON-resistance for the N-MOSFET is typical 90mΩ.
15
FN7650.1
August 25, 2010