ISL78419ARZ-T Datasheet, PDF (15/20 Pages) Intersil Corporation – Integrated Automotive TFT-LCD Power Supply Regulator

SCL FROM
MASTER
SDA OUTPUT FROM
TRANSMITTER
ISL78419
1
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
S
WRITE
T
A
R
IDENTIFICATION
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
0 1 0 1 00 0 0 0 0 0 0 0 0 ^X0
SIGNALS FROM
THE ISL78419
A
A
A
C
C
C
K
K
K
FIGURE 17. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R _{BYTE WITH}
T
R/W = 1
A
A
C
C
K
K
S
T
O
P
SIGNAL AT SDA 0 1 0 1 0 0 0 0 0 0 0 0 0 0 _X 0
0 1 0 1 00 0 1
A
A
A
SIGNALS FROM
C
C
C
THE SLAVE
K
K
K
FIGURE 18. READ SEQUENCE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
Write Operation
A write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition (see Figure 17). After each of the three bytes, the
ISL78419 responds with an ACK. At this time, if the Data Byte is
to be written only to volatile registers, the device enters its
standby state. If the Data Byte is to be written also to non-volatile
memory, the ISL78419 begins its internal write cycle to
non-volatile memory. During the internal non-volatile write cycle,
the device ignores transitions at the SDA and SCL pins and the
SDA output is at high impedance state. When the internal
non-volatile write cycle is completed, the ISL78419 enters its
standby state. The byte at address 02h determines if the Data
Byte is to be written to volatile and/or non-volatile memory.
Data Protection
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile and
non-volatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0 or 2, the Data Byte is transferred to the Wiper
Register (WR) or to the Access Control Register respectively, at
the falling edge of the SCL pulse that loads the last bit (LSB) of
the Data Byte. If the Address Byte is 0, and the Access Control
Register is all zeros (default), then the STOP condition initiates
the internal write cycle to non-volatile memory.
TABLE 8. I²C INTERFACE SPECIFICATION
PARAMETER
MIN TYP MAX
SDA and SCL Rise Time
1000
SDA and SCL Fall Time
300
I²C Bus Capacitive Load
400
UNITS
ns
ns
pF
15
FN8292.2
January 24, 2014