ISL6548A Datasheet, PDF (15/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6548A
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6548A requires 2 N-Channel power MOSFETs for
switching power. These should be selected based upon
r_DS(ON), gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching
losses when the converter is sinking current (see the
equations below). These equations assume linear voltage-
current transitions and do not adequately model power loss
due the reverse-recovery of the upper and lower MOSFET’s
body diode. The gate-charge losses are dissipated in part by
the ISL6548A and do not significantly heat the MOSFETs.
However, large gate-charge increases the switching interval,
t_SW which increases the MOSFET switching losses. Ensure
that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
Approximate Losses while Sourcing current
P_UPPER
=
Io²
×
r_D
S
(
O
N)
×
D
+
1_--
2
⋅
I
o
×
V_I
N
×
t_S
W
×
f_s
P_LOWER = Io² x r_DS(ON) x (1 - D)
Approximate Losses while Sinking current
P_UPPER = Io² x r_DS(ON) x D
P_LOWER
=
Io²
×
r_D
S
(ON)
×
(1
–
D)
+
1_--
2
⋅
Io
×
V_I
N
×
t_SW
×
f_s
Where: D is the duty cycle = V_OUT / V_IN,
t_SW is the combined switch ON and OFF time, and
f_s is the switching frequency.
MOSFET Selection - LDO
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in the linear regulator is:
P_LINEAR ≅ I_O × (V_IN – V_OUT)
where I_O is the maximum output current and V_OUT is the
nominal output voltage of the linear regulator.
15
FN9189.1
July 22, 2005