ISL267817 Datasheet, PDF (15/18 Pages) Intersil Corporation – 12-Bit Differential Input 200kSPS SAR ADC

ISL267817
where V₁ is the RMS amplitude of the fundamental and V₂, V₃,
V₄, V₅, and V₆ are the RMS amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
RMS value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the RMS value of
the fundamental. Also referred to as Spurious Free Dynamic
Range (SFDR). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mV_P-P sine wave applied to the common-mode voltage of
+IN and –IN of frequency fs:
CMRR(dB) = 10log(Pfl ⁄ Pfs)
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal +IN – (–IN) (i.e., 0 LSB).
Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal +IN – (–IN) (i.e., – VREF + ½ LSB) or the
last code transition (011...110 to 011...111) from the ideal +IN –
(–IN) (i.e., +VREF – 1½ LSB), after the zero code error has been
adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC +VCC
supply of frequency f_S. The frequency of this input varies from
1kHz to 1MHz.
PSRR(dB) = 10log (Pf ⁄ Pfs)
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f_s in the ADC output.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267817 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267817 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267817 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
15
FN7877.2
April 19, 2012