ISL21440 Datasheet, PDF (15/15 Pages) Intersil Corporation – Micropower Voltage Reference with Comparator

ISL21440
Package Outline Drawing
L8.3x3G
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 5/07
PIN 1 INDEX AREA
B
3.00
3.00
A
0.075 C
4X
6X 0.50 BSC
1.75
TOP VIEW
8X 0.25
0.10 M C A B
1.45
PIN 1 INDEX AREA
1.50
REF
2.20
BOTTOM VIEW
8X 0.40
(8X 0.25)
(8X 0.60)
(6X 0.50 BSC)
(1.75)
(1.45)
(2.20)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL X''
0.75
0.10 C
C
SEATING PLANE
0.08 C
SIDE VIEW
0.20 REF ⁵
c
0~0.05
DETAIL “X”
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to JEDEC STD MO220-D.
4. The configuration of the pin #1 identifier is optional, but must be located
within the zone indicated. The pin #1 identifier may be either a mold or
mark feature.
5. Tiebar shown (if present) is a non-functional feature.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6532.1
March 2, 2010