HI5728 Datasheet, PDF (15/17 Pages) Intersil Corporation – 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter

Timing Diagrams
HI5728
CLK
50%
D9-D0
I_OUT
1 LSB ERROR BAND
t_SETT
t_PD
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
t_PW1
t_PW2
CLK
D9-D0
t_SU
t_SU
t_HLD
t_PD
V
GLITCH AREA = ¹/₂ (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t_SU
t_HLD
t_HLD
t_SETT
50%
I_OUT
t_PD
t_SETT
t_PD
t_SETT
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25Ω due to the
parallel resistance of the output 50Ω and the oscilloscope’s
50Ω input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as ‘Output Settling Time.’
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