X9470 Datasheet, PDF (14/24 Pages) Xicor Inc. – RF Power Amplifier (PA) Bias Controller

Figure 3. Bias Adjustment Block Diagram
X9470
RW_BIAS
RH_BIAS
RL_BIAS
Legend
External pin/signal
Internal node/signal
SCL
CS
Gate Bias
Op Amp
–
V_BIAS (unbuffered) ₊
2
R_BIAS
10kΩ
256-tap
V_BIAS
to LDMOS gate
SHDN
XDCP
Memory and Control ^{INC/DEC is logic HIGH or LOW}
from Sense/Scale Block
WCR (Rbias)
and is used to increment or
decrement the Rbias resistor
3
Bias Register
non-volatile
(XDCP) to adjust the gate voltage.
Power-On Recall
(POR)
U/D
INC
CS
1
INC/DEC
Note:
1) WCR = Wiper Control Register
NON-VOLATILE STORE OF THE BIAS POSITION
The following procedure will store the values for the
Rref and Rbias wiper positions in Non-Volatile mem-
ory. This sequence is intended to be performed after a
BiasLock calibration sequence to simplify storage. If
BiasLock has not been achieved, then the Rbias wiper
position may change when the CS pin is brought high
and SCL begins clocking. See Figure 4 for the actual
sequence.
1. Set the WEL bit with a write command (02h to reg-
ister 0Fh)
2. Peform a calibration and achieve BiasLock. Leave
CS pin high.
3. Write the address byte only (START, followed by
device/slave address and a 0 for a write, see page
19).
4. Perform a STOP command.
5. With SCL still low, bring the CS low. The falling
edge of the CS will initiate the NV write.
The WEL bit may be reset afterwards to prevent fur-
ther NV writes.
INC/DEC FUNCTION
The INC/DEC pin is an open-drain logic output that
tracks the activity of the increment/decrement compar-
ator. A logic HIGH at INC/DEC indicates that the I_DQ
did not rise up to the desired setting indicated by V_REF
while a logic LOW at the INC/DEC pin indicates that
the IDQ is higher than the desired setting.
INC/DEC is used as an internal control signal as well.
As an example, when INC/DEC is LOW, the Bias
Adjustment Circuit Block will start to move the Rbias
resistor wiper towards the RL_BIAS terminal end when
CS is HIGH and SCL is clocking. Consequently, the
V_BIAS voltage will decrease, and the I_DQ decreases to
meet the desired V_REF setting.
The INC/DEC signal can also be used to detect a
damaged RF power FET. For instance, If INC/DEC
stays HIGH during and after a calibration sequence it
may indicate that the RF power FET has failed. This
indicator can also be used with a level sense on the
V_OUT pin to perform diagnostics.
SHUTDOWN MECHANISM
This hardware control shutdown pin (SHDN) will pull
the voltage of V_BIAS to VSS with an internal pull down
resistor. When shutdown is disabled (V_BIAS is active
when SHDN is LOW), the V_BIAS voltage will move to
the previous desired bias voltage.
It will take less than a microsecond to enable the inter-
nal output buffer depending on the loading condition at
the V_BIAS pin.
OUTPUT (V_BIAS)
V_BIAS is a buffered output of RW_BIAS (wiper output). It
can deliver a high current for driving up to typically 1nF
capacitive loading with stable performance and fast
settling time.
14
FN8204.0
March 8, 2005