X1205 Datasheet, PDF (14/22 Pages) Xicor Inc. – Real Time Clock/Calendar

X1205
Figure 7. Slave Address, Word Address, and Data Bytes
Slave Address Byte
1
1
0
1
1
1
1
R/W _{Byte 0}
Word Address 1
0
0
0
0
0
0
0
0
Byte 1
Word Address 0
A7
A6
A5
A4
A3
A2
A1
A0
Byte 2
Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Byte 3
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the CCR.
(Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceding operations to enable the write operation. See
“Writing to the Clock/Control Registers.” Upon receipt
of each address byte, the X1205 responds with an
acknowledge. After receiving both address bytes the
X1205 awaits the eight bits of data. After receiving the
8 data bits, the X1205 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1205 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 8.
Figure 8. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals From
The Slave
S
t
a
r
Slave
t ^Address
Word
Address 1
Word
Address 0
S
t
o
Data
p
1101 1 110 00000000
A
A
A
A
C
C
C
C
K
K
K
K
14
FN8097.2
September 23, 2005