ISL98001 Datasheet, PDF (14/31 Pages) Intersil Corporation – Triple Video Digitizer with Digital PLL

Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
0x09
Red Offset (0x80)
0x0A
Green Offset (0x80)
0x0B
Blue Offset (0x80)
0x0C
Offset DAC Configuration (0x00)
0x0D
AFE Bandwidth (0x2E)
0x0E
0x0F
0x10
PLL Htotal MSB (0x03)
PLL Htotal LSB (0x20)
PLL Sampling Phase (0x00)
0x11
0x12
PLL Pre-coast (0x04)
PLL Post-coast (0x04)
ISL98001
BIT(S) FUNCTION NAME
DESCRIPTION
7:0 Red Offset
7:0 Green Offset
7:0 Blue Offset
ABLC enabled: digital offset control. A 1LSB change in
this register will shift the ADC output by 1 LSB.
ABLC disabled: analog offset control. These bits go to
the upper 8-bits of the 10-bit offset DAC. A 1LSB
change in this register will shift the ADC output
approximately 1 LSB (Offset DAC range = 0) or
0.5LSBs (Offset DAC range = 1).
0x00 = min DAC value or -0x80 digital offset,
0x80 = mid DAC value or 0x00 digital offset,
0xFF = max DAC value or +0x7F digital offset
0 Offset DAC Range 0: ±½ ADC fullscale (1 DAC LSB ~ 1 ADC LSB)
1: ±¼ ADC fullscale (1 DAC LSB ~ ½ ADC LSB)
1 Reserved
Set to 0.
3:2 Red Offset DAC
LSBs
5:4 Green Offset DAC
LSBs
These bits are the LSBs necessary for 10-bit manual
offset DAC control.
Combine with their respective MSBs in registers 0x09,
0x0A, and 0x0B to achieve 10-bit offset DAC control.
7:6 Blue Offset DAC
LSBs
0 Unused
Value doesn’t matter
3:1 AFE BW
3dB point for AFE lowpass filter
000b: 100MHz
111b: 780MHz (default)
7:4 Peaking
0x0: Peaking off
0x1: Moderate peaking
0x2: Maximum recommended peaking (default)
Values above 2 are not recommended.
5:0 PLL Htotal MSB
7:0 PLL Htotal LSB
14-bit HTOTAL (number of active pixels) value
The minimum HTOTAL value supported is 0x200.
HTOTAL to PLL is updated on LSB write only.
5:0 PLL Sampling Phase Used to control the phase of the ADC’s sample point
relative to the period of a pixel. Adjust to obtain
optimum image quality. One step = 5.625° (1.56% of
pixel period).
7:0 Pre-coast
Number of lines the PLL will coast prior to the start of
VSYNC.
7:0 Post-coast
Number of lines the PLL will coast after the end of
VSYNC.
14
FN6148.5
September 21, 2010