ISL78322 Datasheet, PDF (14/18 Pages) Intersil Corporation – Dual 2A/1.7A Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator

ISL78322
Theory of Operation
The ISL78322 is a dual 2A/1.7A step-down switching regulator
optimized for battery-powered or mobile applications. The
regulator operates at 2.25MHz fixed switching frequency under
heavy load condition to allow small external inductor and
capacitors to be used for minimal printed circuit board (PCB)
area. At light load, the regulator reduces the switching frequency,
unless forced to the fixed frequency, to minimize the switching
loss and to maximize the battery life. The two channels are 180°
out-of-phase operation. The quiescent current when the outputs
are not loaded is typically only 40µA. The supply current is
typically only 6.5µA when the regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin LOW (<0.4V) forces the converter into PWM
mode in the next switching cycle regardless of output current.
Each of the channels of the ISL78322 employ the current-mode
pulse-width modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting shown in the “Block
Diagram” on page 3. The current loop consists of the oscillator,
the PWM comparator COMP, current sensing circuit, and the
slope compensation for the current loop stability. The current
sensing circuit consists of the resistance of the P-channel
MOSFET when it is turned on and the current sense amplifier
CSA1 (or CSA2 on Channel 2). The gain for the current sensing
circuit is typically 0.32V/A. The control reference for the current
loops comes from the error amplifier EAMP of the voltage loop.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA1 (or CSA2) and the
compensation slope (0.9V/µs) reaches the control reference of the
current loop, the PWM comparator COMP sends a signal to the
PWM logic to turn off the P-MOSFET and to turn on the N-channel
MOSFET. The N-MOSFET stays on until the end of the PWM cycle.
Figure 44 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA_ output.
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.6V
reference voltage to the voltage control loop. The feedback signal
comes from the V_FB pin. The soft-start block only affects the
operation during the start-up and will be discussed separately
shortly. The error amplifier is a transconductance amplifier that
converts the voltage error signal to a current output. The voltage
loop is internally compensated with the 27pF and 250kΩ RC
network. The maximum EAMP voltage output is precisely
clamped to 1.8V.
V_EAMP
V_CSA
DUTY
CYCLE
I_L
V_OUT
FIGURE 44. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin HIGH (>1.5V) enables the converter into
PFM mode at low load. The ISL78322 enters a pulse-skipping
mode at light load to minimize the switching loss by reducing the
switching frequency. Figure 45 illustrates the skip-mode
operation. A zero-cross sensing circuit shown in the “Block
Diagram” on page 3, monitors the N-MOSFET current for zero
crossing. When 16 consecutive cycles of the N-MOSFET crossing
zero are detected, the regulator enters the skip mode. During the
16 detecting cycles, the current in the inductor is allowed to
become negative. The counter is reset to zero when the current in
any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in the “Block Diagram”
on page 3. Each pulse cycle is still synchronized by the PWM
clock. The P-MOSFET is turned on at the clock and turned off
when its current reaches the threshold of 600mA. As the average
inductor current in each cycle is higher than the average current
of the load, the output voltage rises cycle over cycle. When the
output voltage reaches 1.5% above the nominal voltage, the
P-MOSFET is turned off immediately. Then the inductor current is
fully discharged to zero and stays at zero. The output voltage
reduces gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-MOSFET will be turned on again at the clock, repeating the
previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
Synchronization Control
The frequency of operation can be synchronized up to 8MHz by
an external signal applied to the SYNC pin. The 1st falling edge
on the SYNC triggered the rising edge of the PWM ON pulse of
Channel 1. The 2nd falling edge of the SYNC triggers the rising
edge of the PWM ON pulse of the Channel 2. This process
alternates indefinitely allowing 180° output phase operation
between the two channels. The internal frequency will take
control when the divided external sync is lower than 2.25MHz.
The falling edge on the SYNC triggers the rising edge of the PWM
ON pulse.
Submit Document Feedback ₁₄
FN7908.2
August 26, 2014