ISL6744A_14 Datasheet, PDF (14/18 Pages) Intersil Corporation – Intermediate Bus PWM Controller

ISL6744A
13.5
13.0
12.5
12.0
11.5
11.0
10.5
42 43 44 45 46 47 48 49 50 51 52 53
INPUT VOLTAGE (V)
FIGURE 12. LINE REGULATION AT I_OUT = 1A
Waveforms
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage ripple and noise at a 5A.
FIGURE 14. FET DRAIN-SOURCE VOLTAGE
FIGURE 13. OUTPUT RIPPLE AND NOISE - 20MHz BW
Figures 14 and 15 show the voltage waveforms at the
switching node shared by the upper FET source and the
lower FET drain. In particular, Figure 15 shows near ZVS
operation at 5A of load when the upper FET is turning off
and the lower FET is turning on. ZVS operation occurs
completely, implying that all the energy stored in the node
capacitance has been recovered. Figure 16 shows the
switching transition between outputs, OUTA and OUTB
during steady state operation. The deadtime duration of
46.9ns is clearly shown.
A 2.7V zener is added between the Vdd pins of ISL6700 and
ISL6744, in order to ensure that the PWM turns on only after
the driver has turned on, thereby ensuring the soft-start
function. Figure 17 shows the soft-start operation.
14
FIGURE 15. FET D-S VOLTAGE NEAR-ZVS TRANSITION
FIGURE 16. OUTA - OUTB TRANSITION
FN6554.0
October 8, 2007